Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 813

15.5.3.6.32 Transmit Single Collision Packet Counter (TSCL)
Figure 15-83 describes the definition for the TSCL register.
Offset eTSEC1:0x2_46FC; eTSEC2:0x2_56FC
0
R
W
Reset
Figure 15-83. Transmit Single Collision Packet Counter Register Definition
Table 15-87 describes the fields of the TSCL register.
Bits Name
0–19 — Reserved
20–31 TSCL Transmit single collision packet counter. Increments for each frame transmitted which experienced
exactly one collision during transmission.
15.5.3.6.33 Transmit Multiple Collision Packet Counter (TMCL)
Figure 15-84 describes the definition for the TMCL register.
Offset eTSEC1:0x2_4700; eTSEC2:0x2_5700
0
R
W
Reset
Figure 15-84. Transmit Multiple Collision Packet Counter Register Definition
Table 15-88 describes the fields of the TMCL register.
Bits Name
0–19 — Reserved
20–31 TMCL Transmit multiple collision packet counter. Increments for each frame transmitted which experienced 2–15
collisions (including any late collisions) during transmission as defined using the
Half_Duplex[RETRANSMISSION MAXIMUM] field.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
—
All zeros
Table 15-87. TSCL Field Descriptions
Description
—
All zeros
Table 15-88. TMCL Field Descriptions
Description
Enhanced Three-Speed Ethernet Controllers
Access: Read/Write
19 20
TSCL
Access: Read/Write
19 20
TMCL
31
31
15-95