Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 180

Reset, Clocking, and Initialization
RCWLR Bits
4–7
In PCI host mode, the SPMF field described in
csb_clk:SYS_CLK_IN ratio regardless of the CFG_CLKIN_DIV reset
configuration input value during reset flow.
The SPMF field maximum allowed value is dependent on the value sampled on CFG_CLKIN_DIV during
power-on reset. Table 4-10
are as follows:
4.3.2.2 Reset Configuration Word High Register (RCWHR)
RCWHR is shown in Figure
word high loaded during the reset flow.
Offset 0x0_0904
0 1
PCIHO
Field — PCIARB
ST
16
Field TSEC1M
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
4-14
Table 4-9. System PLL Ratio
Value
Field Name
(Binary)
SPMF 0000
0001
0010
0011
0100
0101
0110
0111–1111
defines the upper limit of SPMF with respect to these values. Values for SPMF
Table 4-10. SPMF Maximum Values
CFG_CLKIN_DIV LBCM
1
0
4-4. This read-only register gets its values according to the reset configuration
2 3 4
CORE
—
DIS
18 19
TSEC2M
Figure 4-4. Reset Configuration Word High Register (RCWHR)
csb_clk : CLKIN (PCI Host Mode)
csb_clk : (PCI_CLK x
(1+~sampled_cfg_clkin_div))
(PCI Agent Mode)
Reserved, should not be set
NOTE
Table 4-9
Maximum SPMF
DDRCM
Value (Decimal)
0 1
0 1
5 6 7 8
BMS BOOTSEQ SWEN
21 22
—
Reserved
Reserved
2 : 1
3 : 1
4 : 1
5 : 1
6 : 1
always selects the
6
3
Access: Read/Write
9 11 12
ROMLOC RLEXT
27 28
TLE LALE
Freescale Semiconductor
13 14 15
— —
29 30 31
—