Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 497

Option Register Attributes
TRLX XACS
0 1
0 1
0 1
1 0
1 0
1 0
1 1
1 1
1 1
1 0
1 0
1 0
1 1
1 1
1 1
1
Times in parentheses are specific for the case LCRR[CLKDIV] = 2; other times apply to all CLKDIV values.
10.4.2.3 Chip-Select Assertion Timing
The banks selected to work with the GPCM support an option to drive the LCSn signal with different
timings (with respect to the external address/data bus). LCSn can be driven in any of the following ways:
• Simultaneous with the latched memory address. (This refers to the externally latched address and
not the address timing on LAD. That is, the chip select does not assert during LALE).
• One quarter of a clock cycle later (for LCRR[CLKDIV] = 4, 8).
• One half of a clock cycle later (for LCRR[CLKDIV] = 2, 4, or 8).
• One clock cycle later (for LCRR[CLKDIV] = 4), when OR
• Two clock cycles later (for LCRR[CLKDIV] = 2, 4, or 8), when OR
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 10-33. GPCM Write Control Signal Timing (continued)
ACS CSNT t
AWCS
00 1 0
10 1 1
11 1 2
00 0 0
10 0 1¼
(1½)
11 0 1½
00 0 0
10 0 2
11 0 3
00 1 0
10 1 1¼
(1½)
11 1 1½
00 1 0
10 1 2
11 1 3
Signal Timing (LCLK clock cycles)
t t
CSWP AWE
2+SCY 1
¾+SCY 1
(½+SCY)
¾+SCY 2
(½+SCY)
2+2×SCY 1
1¾+2×SCY 2
(2+2×SCY)
1½+2×SCY 2
2+2×SCY 1
1+2×SCY 2
1+2×SCY 3
3+2×SCY 1
1½+2×SCY 2
1¼+2×SCY 2
(1+2×SCY)
3+2×SCY 1
¾+2×SCY 2
(½+2×SCY)
¾+2×SCY 3
(½+2×SCY)
[XACS] = 1.
n
Enhanced Local Bus Controller
1
t t
WEN WC
¼ 2+SCY
(0)
0 1¾+SCY
(1½+SCY)
0 2¾+SCY
(2½+SCY)
0 2+2×SCY
0 3+2×SCY
0 3+2×SCY
0 2+2×SCY
0 3+2×SCY
0 4+2×SCY
1¼ 3+2×SCY
(1)
0 2¾+2×SCY
(2½+2×SCY)
0 2¾+2×SCY
(2½+2×SCY)
1¼ 3+2×SCY
(1)
0 2¾+2×SCY
(2½+2×SCY)
0 3¾+2×SCY
(3½+2×SCY)
[XACS] = 1.
n
10-49