Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 413

Table 9-12 describes the DDR_SDRAM_CFG fields.
Bits Name
0 MEM_EN
1 SREN
2 —
3 RD_EN
4 —
5–7 SDRAM_TYPE
8–9 —
10 DYN_PWR
11–12 DBW
13 8_BE
14 NCAP
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 9-12. DDR_SDRAM_CFG Field Descriptions
DDR SDRAM interface logic enable.
0 SDRAM interface logic is disabled.
1 SDRAM interface logic is enabled. Must not be set until all other memory configuration
parameters have been appropriately configured by initialization code.
Self refresh enable (during sleep).
0 SDRAM self refresh is disabled during sleep. Whenever self-refresh is disabled, the system is
responsible for preserving the integrity of SDRAM during sleep.
1 SDRAM self refresh is enabled during sleep.
Reserved. Must be cleared.
Registered DRAM module enable. Specifies the type of DRAM module used in the system.
0 Indicates unbuffered DRAM modules.
1 Indicates registered DRAM modules.
Note: RD_EN and 2T_EN must not both be set at the same time.
Reserved
Type of SDRAM device to be used. This field is used when issuing the automatic hardware
initialization sequence to DRAM through Mode Register Set and Extended Mode Register Set
commands. Default value is 010 designating DDR1 SDRAM.
000–001Reserved
010 DDR1 SDRAM
011 DDR2 SDRAM
100 Reserved
101 Reserved
110 Reserved
111 Reserved
Reserved
Dynamic power management mode
0 Dynamic power management mode is disabled.
1 Dynamic power management mode is enabled. If there is no ongoing memory activity, the
SDRAM CKE signal is negated.
DRAM data bus width.
00 Reserved
01 32-bit bus is used
10 16-bit bus is used
11 Reserved
8-beat burst enable.
0 4-beat bursts are used on the DRAM interface.
1 8-beat bursts are used on the DRAM interface.
Note: DDR1 (SDRAM_TYPE = 010) must use 8-beat bursts when using 32-bit bus mode (32_BE =
1) and 4-beat bursts when using 64-bit bus mode; DDR2 (SDRAM_TYPE = 011) must use
4-beat bursts, even when using 32-bit bus mode
Non-concurrent auto-precharge. Some older DDR DRAMs do not support concurrent auto
precharge. If one of these devices is used, then this bit needs to be set if auto precharge is used.
0 DRAMs in system support concurrent auto-precharge.
1 DRAMs in system do not support concurrent auto-precharge.
Description
DDR Memory Controller
9-19