Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 467

Bits Name
19 BCTLD Buffer control disable. Disables assertion of LBCTL during access to the current memory bank.
0 LBCTL is asserted upon access to the current memory bank.
1 LBCTL is not asserted upon access to the current memory bank.
20–22 — Reserved
23 BI Burst inhibit. Indicates if this memory bank supports burst accesses.
0 The bank supports burst accesses.
1 The bank does not support burst accesses. The selected UPM executes burst accesses as a series of
single accesses.
24–28 — Reserved
29 TRLX Timing relaxed. Works in conjunction with EHTR to extend hold time on read accesses.
30 EHTR Extended hold time on read accesses. Indicates with TRLX how many cycles are inserted between a read
access from the current bank and the next access.
TRLX EHTR
0
0
1
1
31 EAD External address latch delay. Allow extra bus clock cycles when using external address latch (LALE).
0 No additional bus clock cycles (LALE asserted for one bus clock cycle only)
1 Extra bus clock cycles are added (LALE is asserted for the number of bus clock cycles specified by
LCRR[EADC]).
10.3.1.3 UPM Memory Address Register (MAR)
Figure 10-6 shows the fields of the UPM memory address register (MAR).
Offset 0x0_5068
0
R
W
Reset
Table 10-10 describes the MAR fields.
Bits Name
0–31 A Address that can be output to the address signals under control of the AMX bits in the UPM RAM word.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
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Table 10-9. OR UPM Field Descriptions (continued)
n
0 The memory controller generates normal timing. No additional cycles are inserted.
1 1 idle clock cycle is inserted.
0 4 idle clock cycles are inserted.
1 8 idle clock cycles are inserted.
Figure 10-6. UPM Memory Address Register (MAR)
Table 10-10. MAR Field Descriptions
Description
Meaning
A
All zeros
Description
Enhanced Local Bus Controller
Access: Read/Write
10-19
31