Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 357

7.4 Differences Between Cores
The e300 core has similar functionality to the G2_LE core.
the G2_LE and the e300.
e300 Core
New HID0 bits
New HID1 bits
New HID2 bits
New PVR register value
New IBCR and DBCR bits
—
L1 cache parity
MEI or MESI coherency
protocols
Instruction cancel extension
Instruction fetch bursts to
caching-inhibited space
Instruction cache way
protection
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 7-8. Differences Between e300 and G2_LE Cores
G2_LE Core
—
—
—
—
—
16-Kbyte, four-way,
set-associative, instruction
and data caches
—
MEI protocol only
—
Single-beat instruction
fetches to caching-inhibited
space
—
Table 7-8 describes the differences between
The e300 core has a new HID0 bit defined to enable cache parity
error reporting (ECPE).
The e300 core has new HID1 bits defined to extend the number of
PLL configuration signals to seven (PC5, PC6).
The e300 core has new HID2 bits defined to support instruction
fetch bursting (IFEB), MESI coherency protocol (MESI),
instruction fetch cancels (IFEC), data cache queue sharing
(EBQS), pipelining extension (EBPX), additional cache way
locking (IWLCK and DWLCK), and instruction cache way
protection (ICWP).
The processor version register values differ.
The e300 core has new IBCR[IABRSTAT, IABR2STAT] and
DBCR[DABR1STAT, DABR2STAT] fields to provide instruction and
data address breakpoint status.
Some e300 cores may have different cache sizes than the G2_LE.
See the e300 PowerPC Core Reference Manual for detailed
information.
The e300 core supports parity for both instruction and data
caches; the G2_LE does not support cache parity.
The e300 supports two coherency protocols: MEI and MESI; the
G2_LE only supports the MEI protocol.
The e300 instruction cancel mechanism improves utilization of
instruction cache by supporting 'hits-under-cancels' and
'misses-under-cancels'; the G2_LE requires the cancel to
complete before new instruction fetches can begin.
The e300's instruction fetch burst extension allows all
caching-inhibited instruction fetches to be performed on the bus as
burst transactions, even though the instructions are not cached.
This improves performance for instruction space that is
caching-inhibited, because up to eight instructions are returned
with one bus operation. The G2_LE core must use single-beat
instruction fetches for caching-inhibited space, returning only two
instructions per bus operation.
The e300 core can protect locked ways in the instruction cache
from invalidation; the G2_LE does not support instruction cache
way protection.
e300 Processor Core Overview
Impact
7-39