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Freescale Semiconductor MPC8358E Hardware Specificftion

Powerquicc ii pro processor revision 2.x tbga silicon
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Freescale Semiconductor
Technical Data
MPC8360E/MPC8358E
PowerQUICC II Pro Processor
Revision 2.x TBGA Silicon
Hardware Specifications
This document provides an overview of the MPC8360E/58E
PowerQUICC II Pro processor revision 2.x TBGA features,
including a block diagram showing the major functional
components. This device is a cost-effective, highly
integrated communications processor that addresses the
needs of the networking, wireless infrastructure, and
telecommunications markets. Target applications include
next generation DSLAMs, network interface cards for 3G
base stations (Node Bs), routers, media gateways, and high
end IADs. The device extends current PowerQUICC II Pro
offerings, adding higher CPU performance, additional
functionality, faster interfaces, and robust interworking
between protocols while addressing the requirements related
to time-to-market, price, power, and package size. This
device can be used for the control plane and also has data
plane functionality.
For functional characteristics of the processor, refer to the
MPC8360E PowerQUICC II Pro Integrated
Communications Processor Family Reference Manual,
Rev. 3.
To locate any updates for this document, refer to the
MPC8360E product summary page on our website listed on
the back cover of this document or contact your Freescale
sales office.
© 2011 Freescale Semiconductor, Inc. All rights reserved.
Document Number: MPC8360EEC
Contents
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Electrical Characteristics . . . . . . . . . . . . . . . . . . 8
3. Power Characteristics . . . . . . . . . . . . . . . . . . . 13
4. Clock Input Timing . . . . . . . . . . . . . . . . . . . . . 15
5. RESET Initialization . . . . . . . . . . . . . . . . . . . . 17
6. DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . 20
7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
MII Management . . . . . . . . . . . . . . . . . . . . . . . 28
9. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
10. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
2
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
12. PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
13. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
14. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
15. IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
16. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
17. TDM/SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
18. UTOPIA/POS . . . . . . . . . . . . . . . . . . . . . . . . . 62
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
20. USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
21. Package and Pin Listings . . . . . . . . . . . . . . . . . 68
22. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
23. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
24. System Design Information . . . . . . . . . . . . . . 102
25. Ordering Information . . . . . . . . . . . . . . . . . . . 106
26. Document Revision History . . . . . . . . . . . . . 107
Rev. 4, 01/2011

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Summary of Contents for Freescale Semiconductor MPC8358E

  • Page 1: Table Of Contents

    MPC8360E product summary page on our website listed on 26. Document Revision History ... . . 107 the back cover of this document or contact your Freescale sales office. © 2011 Freescale Semiconductor, Inc. All rights reserved.

  • Page 2: Overview

    32-bit DDR memory controller for control plane processing and the other for data plane processing. The MPC8358E has a single DDR SDRAM memory controller. The MPC8360E/58E also offers a 32-bit PCI controller, a flexible local bus, and a dedicated security engine.
  • Page 3 • e300 PowerPC processor core (enhanced version of the MPC603e core) — Operates at up to 667 MHz (for the MPC8360E) and 400 MHz (for the MPC8358E) — High-performance, superscalar processor core — Floating-point, integer, load/store, system register, and branch processing units —...
  • Page 4 – Transparent up to 70-Mbps full-duplex – HDLC up to 70-Mbps full-duplex – HDLC BUS up to 10 Mbps 1.SMII or SGMII media-independent interface is not currently supported. MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 5 31/124 MultiPHY — Two serial peripheral interfaces (SPI); SPI2 is dedicated to Ethernet PHY management — Eight TDM interfaces on the MPC8360E and four TDM interfaces on the MPC8358E with 1-bit mode for E3/T3 rates in clear channel — Sixteen independent baud rate generators and 30 input clock pins for supplying clocks to UCC and MCC serial channels (MCC is only available on the MPC8360E) —...
  • Page 6 — On the MPC8360E, the DDR buses can be configured as two 32-bit buses or one 64-bit bus; on the MPC8358E, the DDR bus can be configured as a 32- or 64-bit bus — 32- or 64-bit data interface, up to 333 MHz (for the MPC8360E) and 266 MHz (for the MPC8358E) data rate —...
  • Page 7 — External and internal interrupts directed to communication processor — Redirects interrupts to external INTA pin when in core disable mode — Unique vector number for each interrupt source MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...

  • Page 8: Electrical Characteristics

    MPC8360E/58E. The device is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer design specifications. MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...

  • Page 9: Absolute Maximum Ratings

    Figure 6. OV on the PCI interface may overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation, as shown in Figure MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 10 , on the 600/333/400 MHz and 500/333/500 MHz on rev. 2.0 silicon is 0° to 70 °C. Refer to Errata General9 in Chip Errata for the MPC8360E, Rev. 1 . MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 11 4 ns (Max) 62.5 ns +3.6 V 7.1 V p-to-p Undervoltage Waveform (Min) –3.5 V Figure 4. Maximum AC Waveforms on PCI interface for 3.3-V Signaling MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...

  • Page 12: Power Sequencing

    In the case where the core voltage is applied first, the core voltage supply must rise to 90% of its nominal value before the I/O supplies reach 0.7 V, see Figure MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...

  • Page 13: Power Characteristics

    Unit Notes Frequency (MHz) Frequency (MHz) Frequency (MHz) 2, 3, 5 2, 3, 4 2, 3, 4 3, 6, 7, 8 3, 6, 7, 8 MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 14 4. Maximum power is based on a voltage of V = 1.2 V, WC process, a junction T = 105°C, and an artificial smoke test. MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...

  • Page 15: Clock Input Timing

    This should be enforced especially on clock signals. Rise time refers to signal transitions from 10% to 90% of V ; fall time refers to transitions from 90% to 10% of V MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...

  • Page 16: Dc Electrical Characteristics

    5. The CLKIN/PCI_CLK driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low to allow cascade-connected PLL-based devices to track CLKIN drivers with the specified jitter. MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...

  • Page 17: Reset Initialization

    Input low voltage — –0.3 μA Input current — — ±10 Output high voltage = –8.0 mA — Output low voltage = 8.0 mA — MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 18 CLKIN. It is only valid when the device is in PCI host mode. See the CLKIN MPC8360E PowerQUICC II Pro Integrated Communications Processor Family Reference Manual for more details. 3. POR config signals consists of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV. MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 19 2 × F UTOPIA L2 50 (max) 2 × F POS-PHY L2 50 (max) HDLC bus 10 (max) — 8/3 × F HDLC/transparent 50 (max) 2, 3 MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...

  • Page 20: Ddr And Ddr2 Sdram

    Output high current (V = 1.420 V) –13.4 — — Output low current (V = 0.280 V) 13.4 — — μA input leakage current — ±10 — VREF MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 21 . This rail should track variations in the DC level of MV ≤ ≤ 4. Output leakage is measured with all outputs disabled, 0 V MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 22 1. Maximum possible skew between a data strobe (MDQS[n]) and any corresponding bit of data (MDQ[8n + {0...7}] if 0 ≤ n ≤ 7) or ECC (MECC[{0...7}] if n = 8). MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 23 Parameter Symbol Unit Notes MCK[n] cycle time, (MCK[n]/MCK[n] crossing) Skew between any MCK to ADDR/CMD AOSKEW 333 MHz –1.0 266 MHz –1.1 200 MHz –1.2 MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 24 MDQ/MECC/MDM output hold with respect to MDQS — DDKHDX 333 MHz DDKLDX 266 MHz 200 MHz –0.5 × t –0.5 × t MDQS preamble start – 0.6 + 0.6 DDKHMP MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 25 0.6 ns. In rev. 2.0 silicon, due to errata, t minimum is DDKHMH DDKHMH –0.9 ns. Refer to Errata DDR18 in Chip Errata for the MPC8360E, Rev. 1 . MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 26 Notes ± 0.31 V ± 0.25 V 0.5 × GV 0.5 × GV Notes: 1. Data input threshold measurement point. 2. Data output measurement point. MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...

  • Page 27: Duart

    ≤ OV μA — ±10 Note: 1. Note that the symbol V , in this case, represents the OV symbol referenced in Table 1 Table MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...

  • Page 28: Ucc Ethernet Controller: Three-Speed Ethernet, Mii Management

    2.5 V. The RGMII and RTBI interfaces follow the Reduced Gigabit Media-Independent Interface (RGMII) Specification Version 1.3. The RMII interface follows the RMII Consortium RMII Specification Version 1.2. MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 29 GTXH/tGTX GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay — — GTKHDX — GTKHDV GTX_CLK clock rise time, (20% to 80%) — — — GTXR MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 30 — — — GRDVKH RXD[7:0], RX_DV, RX_ER hold time to RX_CLK — — GRDXKH RX_CLK clock rise time, (20% to 80%) — — — GRXR MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 31 — TX_CLK clock period 100 Mbps — — TX_CLK duty cycle — MTXH TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay — MTKHDX — MTKHDV MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 32 RXD[3:0], RX_DV, RX_ER setup time to RX_CLK 10.0 — — MRDVKH RXD[3:0], RX_DV, RX_ER hold time to RX_CLK 10.0 — — MRDXKH RX_CLK clock rise time, (20% to 80%) — MRXR MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 33 MII receive AC timing diagram. MRXR RX_CLK MRXH MRXF RXD[3:0] RX_DV Valid Data RX_ER MRDVKH MRDXKH Figure 14. MII Receive AC Timing Diagram MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 34 R (rise) or F (fall). Figure 15 shows the RMII transmit AC timing diagram. RMXR REF_CLK RMXH RMXF TXD[1:0] TX_EN RMTKHDX Figure 15. RMII Transmit AC Timing Diagram MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 35 RMII receive AC timing diagram. RMXR REF_CLK RMXH RMXF RXD[1:0] CRS_DV Valid Data RX_ER RMRDVKH RMRDXKH Figure 17. RMII Receive AC Timing Diagram MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 36 MPC8360E, Rev. 1 . Figure 18 shows the TBI transmit AC timing diagram. TTXR GTX_CLK TTXH TTXF TXD[7:0] TX_EN TX_ER TTKHDX Figure 18. TBI Transmit AC Timing Diagram MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 37 TBI receive AC timing diagram. TRXR PMA_RX_CLK1 TRXH TRXF RCG[9:0] Even RCG Odd RCG TRDVKH TRDXKH SKTRX PMA_RX_CLK0 TRXH TRDXKH TRDVKH Figure 19. TBI Receive AC Timing Diagram MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 38 0.75 ns for UCC1 and UCC2 option 1 and 0.85 for UCC2 option 2. SKRGTKHDV Refer to Errata QE_ENET10 in Chip Errata for the MPC8360E, Rev. 1 . UCC1 does meet t minimum for rev. 2.1 SKRGTKHDX silicon. MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 39 Output high voltage = –1.0 mA = Min 2.10 + 0.3 Output low voltage = 1.0 mA = Min 0.50 Input high voltage — 2.00 — MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 40 3. This parameter is dependent on the ce_clk speed (that is, for a ce_clk of 200 MHz, the delay is 90 ns and for a ce_clk of 300 MHz, the delay is 63 ns). MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...

  • Page 41: Local Bus

    3. Inputs need to be stable at least one TMR clock. Local Bus This section describes the DC and AC electrical specifications for the local bus interface of the MPC8360E/58E. MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 42 Local bus clock to address valid for LAD — LBKHOV3 Output hold from local bus clock (except LAD/LDP and LALE) — LBKHOX1 Output hold from local bus clock for LAD/LDP — LBKHOX2 MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 43 LALE output fall to LAD output transition (LATCH hold time) — LBOTOT2 LALE output fall to LAD output transition (LATCH hold time) — LBOTOT3 Local bus clock to output valid — LBKHOV MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 44 Figure 22 provides the AC test load for the local bus. = 50 Ω Output = 50 Ω Figure 22. Local Bus C Test Load MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 45 LBIXKH LBKHOV Output Signals: LSDA10/LSDWE/LSDRAS/ LSDCAS/LSDDQM[0:3] LA[27:31]/LBCTL/LBCKE/LOE/ LBKHOZ LBKHOV Output Signals: LAD[0:31]/LDP[0:3] LBOTOT LALE Figure 24. Local Bus Signals, Nonspecial Signals Only (DLL Bypass Mode) MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 46 LAD[0:31]/LDP[0:3] (DLL Bypass Mode) LBKHOZ LBKHOV UPM Mode Output Signals: LCS[0:3]/LBS[0:3]/LGPL[0:5] Figure 26. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 2 (DLL Bypass Mode) MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 47 LAD[0:31]/LDP[0:3] (DLL Bypass Mode) LBKHOZ LBKHOV UPM Mode Output Signals: LCS[0:3]/LBS[0:3]/LGPL[0:5] Figure 27. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 4 (DLL Bypass Mode) MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...

  • Page 48: Jtag

    = 3.2 mA — Input high voltage — + 0.3 Input low voltage — –0.3 0 V ≤ V ≤ OV μA Input current — ±10 MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 49 4. Non-JTAG signal input timing with respect to t TCLK 5. Non-JTAG signal output timing with respect to t TCLK 6. Guaranteed by design and characterization. MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 50 Boundary Output Data Valid Data Outputs JTKLDZ Boundary Output Data Valid Data Outputs VM = Midpoint Voltage (OV DD /2) Figure 32. Boundary-Scan Timing Diagram MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 51 Data Valid JTKLOV JTKLOX Output Data Valid JTKLOZ Output Data Valid VM = Midpoint Voltage (OV DD /2) Figure 33. Test Access Port Timing Diagram MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...

  • Page 52: I 2 C

    Setup time for a repeated START condition — I2SVKH μs Hold time (repeated) START condition (after this period, the first — I2SXKL clock pulse is generated) Data setup time — I2DVKH MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 53 AC timing diagram for the I C bus. I2CF I2DVKH I2KHKL I2CF I2CL I2SXKL I2CR I2SXKL I2CH I2SVKH I2PVKH I2DXKL Figure 35. I C Bus AC Timing Diagram MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...

  • Page 54: Pci

    6. In rev. 2.0 silicon, due to errata, t minimum is 1 ns. Refer to Errata PCI17 in Chip Errata for the MPC8360E, Rev. 1 . PCIXKH MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 55 Figure 36. PCI AC Test Load Figure 37 shows the PCI input AC timing conditions. PCIVKH PCIXKH Input Figure 37. PCI Input AC Timing Measurement Conditions MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...

  • Page 56: Timers

    2. Timers inputs and outputs are asynchronous to any visible clock. Timers outputs should be synchronized before use by any external synchronous logic. Timers inputs are required to be valid for at least t ns to ensure proper operation. TIWID MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...

  • Page 57: Gpio

    2. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by any external synchronous logic. GPIO inputs are required to be valid for at least t ns to ensure proper operation. PIWID MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...

  • Page 58: Ipic

    PIWID in edge triggered mode. 16 SPI This section describes the DC and AC electrical specifications for the SPI of the MPC8360E/58E. MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 59 (V). Figure 41 provides the AC test load for the SPI. = 50 Ω Output = 50 Ω Figure 41. SPI AC Test Load MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...

  • Page 60: Tdm/Si

    Table 57. TDM/SI DC Electrical Characteristics Characteristic Symbol Condition Unit Output high voltage = –2.0 mA — Output low voltage = 3.2 mA — Input high voltage — + 0.3 MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 61 56. Note that although the specifications generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge. MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...

  • Page 62: Utopia/Pos

    11.5 — UIKHOV UTOPIA outputs—External clock delay 11.6 — UEKHOV UTOPIA outputs—Internal clock high impedance — UIKHOX UTOPIA outputs—External clock high impedance 10.0 — UEKHOX MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 63 UTOPIA timing with external clock. UtopiaCLK (Input) UEIXKH UEIVKH Input Signals: UTOPIA UEKHOV Output Signals: UTOPIA UEKHOX Figure 47. UTOPIA AC Timing (External Clock) Diagram MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...

  • Page 64: Hdlc, Bisync, Transparent, And Synchronous Uart

    = 3.2 mA — Input high voltage — + 0.3 Input low voltage — –0.3 0 V ≤ V ≤ OV μA Input current — ±10 MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...

  • Page 65: Specifications

    HIKHOX internal timing (HI) for the time t memory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X). serial MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 66 HIIXKH HIIVKH Input Signals: (See Note) tHIKHOV Output Signals: (See Note) HIKHOX Note: The clock edge is selectable. Figure 51. AC Timing (Internal Clock) Diagram MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...

  • Page 67: Usb

    /2 of the rising or falling edge of the signals. Figure 52 provide the AC test load for the USB. = 50 Ω Output = 50 Ω Figure 52. USB AC Test Load MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...

  • Page 68: Package And Pin Listings

    1.00 mm Module height (typical) 1.46 mm Solder Balls 62 Sn/36 Pb/2 Ag (ZU package) 95.5 Sn/0.5 Cu/4Ag (VV package) Ball diameter (typical) 0.64 mm MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 69 740-TBGA package. Figure 53. Mechanical Dimensions and Bottom Surface Nomenclature of the TBGA Package MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 70 AR26, AU24, AR23, AR28, AU23, AR22, AU20, AR18 MEMC1_MODT[0:1] AG33, AJ36 MEMC1_MODT[2:3]/ AT1, AK2 MEMC2_MODT[0:1] MEMC1_MWE AT26 — MEMC1_MRAS AT29 — MEMC1_MCAS AT24 — MEMC1_MCS[0:1] AU27, AT27 — MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 71 — C30, D30, E29, B31, C31, D31, D32, A32, C33, B33, F30, E31, A34, D33 PCI_C/BE[3:0]/CE_PF[10:7] E22, B26, E28, F28 — PCI_PAR/CE_PF[11] — PCI_FRAME/CE_PF[12] PCI_TRDY/CE_PF[13] MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 72 LBCTL AD35 — LALE — LGPL0/LSDA10/cfg_reset_source0 AB32 — LGPL1/LSDWE/cfg_reset_source1 AE37 — LGPL2/LSDRAS/LOE AC33 — LGPL3/LSDCAS/cfg_reset_source2 AD34 — LGPL4/LGTA/LUPWAIT/LPBSE AE35 — LGPL5/cfg_clkin_div AF36 — LCKE — MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 73 CE_PA[1:2] AH1, AG5 — CE_PA[3:7] F6, D4, C3, E5, A3 — CE_PA[8] — CE_PA[9:12] F7, B3, E6, B4 — CE_PA[13:14] AG1, AF6 — CE_PA[15] — MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 74 L1, L2, L4, E14, C13, C14, B13 CE_PF[0:3] F14, D13, A12, A11 — Clocks PCI_CLK_OUT[0]/CE_PF[26] — PCI_CLK_OUT[1:2]/CE_PF[27:28] D22, A23 — CLKIN — PCI_CLOCK/PCI_SYNC_IN — PCI_SYNC_OUT/CE_PF[29] JTAG — TRST Test MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 75 DRAM I/O AP28, AR1, AR7, AR10, AR12, AR21, AR25, AR27, voltage AR33, AT15, AT22, AT28, AT33, AU2, AU5, AU16, (2.5 or AU31, AU36 1.8 V) MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 76 AA36, AB2, AB34 and other standard (3.3 V) MVREF1 AN20 — reference voltage MVREF2 AU32 — reference voltage SPARE1 SPARE3 AH32 — SPARE4 AU18 — SPARE5 — MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 77 — AP26 MEMC_MBA[0:1] AU29, AU30 MEMC_MBA[2] AT30 — MEMC_MA[0:14] AU21, AP22, AP21, AT21, AU25, AU26, AT23, — AR26, AU24, AR23, AR28, AU23, AR22, AU20, AR18 MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 78 E22, B26, E28, F28 — PCI_PAR/CE_PF[11] — PCI_FRAME/CE_PF[12] PCI_TRDY/CE_PF[13] PCI_IRDY/CE_PF[14] PCI_STOP/CE_PF[15] PCI_DEVSEL/CE_PF[16] PCI_IDSEL/CE_PF[17] — PCI_SERR/CE_PF[18] PCI_PERR/CE_PF[19] PCI_REQ[0]/CE_PF[20] — PCI_REQ[1]/CPCI_HS_ES/ — CE_PF[21] PCI_REQ[2]/CE_PF[22] — PCI_GNT[0]/CE_PF[23] — PCI_GNT[1]/CPCI1_HS_LED/ — CE_PF[24] MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 79 — LGPL5/cfg_clkin_div AF36 — LCKE — LCLK[0] — LCLK[1]/LCS[6] — LCLK[2]/LCS[7] — LSYNC_OUT — LSYNC_IN — Programmable Interrupt Controller MCP_OUT IRQ0/MCP_IN — IRQ[1]/M1SRCID[4]/M2SRCID[4]/ — LSRCID[4] MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 80 CE_PA[17:21] B16, A16, E17, A17, B17 — CE_PA[22] — CE_PA[23:26] C18, D18, E18, A18 — CE_PA[27:28] AF2, AE6 — CE_PA[29] — CE_PA[30] — CE_PA[31] — MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 81 F14, D13, A12, A11 — Clocks PCI_CLK_OUT[0]/CE_PF[26] — PCI_CLK_OUT[1:2]/CE_PF[27:28] D22, A23 — CLKIN — PCI_CLOCK/PCI_SYNC_IN — PCI_SYNC_OUT/CE_PF[29] JTAG — TRST Test TEST TEST_SEL AU34 QUIESCE — System Control MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 82 AR33, AT15, AT22, AT28, AT33, AU2, AU5, AU16, (2.5 or AU31, AU36 1.8 V) D5, D6 Power for — UCC1 Ethernet interface (2.5 V, 3.3 V) MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 83 AA36, AB2, AB34 and other standard (3.3 V) MVREF1 AN20 — reference voltage MVREF2 AU32 — reference voltage SPARE1 SPARE3 AH32 — SPARE4 AU18 — SPARE5 — MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 84 11. It is recommended that MDIC0 be tied to GND using an 18.2 Ω resistor and MDIC1 be tied to DDR power using an 18.2 Ω resistor for DDR2. MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...

  • Page 85: Clocking

    LBIU Memory Controller Device LSYNC_IN csb_clk to Rest of the Device PCI_CLK/ PCI_SYNC_IN CFG_CLKIN_DIV CLKIN PCI_SYNC_OUT PCI Clock Divider PCI_CLK_OUT[0:2] Figure 54. MPC8360E Clock Subsystem MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 86 PCI_SYNC_OUT and PCI_CLK_OUT. The CFG_CLKIN_DIV configuration input selects whether CLKIN or CLKIN/2 is driven out on the PCI_SYNC_OUT signal. The OCCR[PCIOENn] parameters enable the PCI_CLK_OUTn, respectively. MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 87 Note that lb_clk is not the external local bus or DDRC2 frequency; lb_clk passes through the a LB clock divider to create the external local bus clock outputs (LSYNC_OUT and LCLK[0:2]). The LB clock divider ratio is controlled by LCRR[CLKDIV]. MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 88 The local bus frequency is 1/2, 1/4, or 1/8 of the lb_clk frequency (depending on LCRR[CLKDIV]) which is in turn 1× or 2× the csb_clk frequency (depending on RCWL[LBCM]). MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...

  • Page 89: System Pll Configuration

    RCWL[SVCOD] VCO Divider Reserved NOTE The VCO divider must be set properly so that the system VCO frequency is in the range of 600–1400 MHz. MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 90 0111 1000 1001 1010 10:1 1011 11:1 1100 12:1 1101 13:1 1110 14:1 1111 15:1 0000 16:1 High 0010 High 0011 High 0100 High 0101 MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 91 (PLL off, csb_clk clocks core directly) clocks core directly) ÷ 0001 ÷ 0001 ÷ 0001 ÷ 0001 ÷ 0001 1.5:1 ÷ 0001 1.5:1 ÷ 0001 1.5:1 MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 92 QUICC Engine PLL RCWL[CEPMF] RCWL[CEPDF] Multiplication Factor = RCWL[CEPMF]/ (1 + RCWL[CEPDF]) 00000 × 16 00001 Reserved 00010 × 2 00011 × 3 00100 × 4 MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 93 × 27 11100 × 28 11101 × 29 11110 × 30 11111 × 31 00011 × 1.5 00101 × 2.5 00111 × 3.5 01001 × 4.5 MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 94 The QUICC Engine block VCO frequency is derived from the following equations: ce_clk = (primary clock input × CEPMF) ÷ (1 + CEPDF) QE VCO Frequency = ce_clk × VCO divider × (1 + CEPDF) MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 95 — ∞ ∞ ∞ æ æ 01100 — — ∞ ∞ æ æ 01110 — — — ∞ ∞ æ æ 01111 — — — MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 96 3. Select a suitable QUICC Engine block clock rate from Table 76. Copy the CEPMF and CEPDF configuration bits. 4. Insert the chosen SPMF, COREPLL, CEPMF and CEPDF to the RCWL fields, respectively. MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...

  • Page 97: Thermal

    Junction-to-ambient (@ 2 m/s) on single-layer board (1s) 1, 3 θJMA °C/W Junction-to-ambient (@ 2 m/s) on four-layer board (2s2p) 1, 3 θJMA °C/W Junction-to-board thermal θJB °C/W Junction-to-case thermal θJC MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 98 In addition, the ambient temperature varies widely within the application. For many natural convection and especially closed box applications, the board temperature at the perimeter MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 99 When a heat sink is used, the thermal resistance is expressed as the sum of a junction to case thermal resistance and a case to ambient thermal resistance: θ θ θ where: = junction-to-ambient thermal resistance (°C/W) θ MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 100 Simplified thermal models of the packages can be assembled using the junction-to-case and junction-to-board thermal resistances listed in the thermal resistance table. More detailed thermal models can be made available on request. MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 101 Dow-Corning Electronic Materials 2200 W. Salzburg Rd. Midland, MI 48686-0997 Internet: www.dowcorning.com Shin-Etsu MicroSi, Inc. 888-642-7674 10028 S. 51st St. Phoenix, AZ 85044 Internet: www.microsi.com MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...

  • Page 102: System Design Information

    This section provides electrical and thermal design recommendations for successful application of the MPC8360E/58E. Additional information can be found in MPC8360E/MPC8358E PowerQUICC Design Checklist (AN3097). MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...

  • Page 103: System Clocking

    , and LV pins of the device. These decoupling capacitors should receive their power from separate V , OV , GV , LV , and GND MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 104 R and R are designed to be close to each other in value. Then, Z = (R )/2. MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 105 HRESET is asserted, is latched when HRESET deasserts, at which time the input receiver is disabled and the I/O circuit takes on its normal function. Careful board layout with stubless connections to these MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...

  • Page 106: Ordering Information

    Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this specification support all core frequencies. Additionally, parts addressed by part number specifications may support other maximum core frequencies. MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...

  • Page 107: Document Revision History

    CLKIN/2 is driven out on the PCI_CLK_OUTn signals.” • In Section 22.1, “System PLL Configuration,” updated the system VCO frequency conditions. • In Table 80, added extended temperature characteristics. 12/2007 Initial release. MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor...
  • Page 108 Headquarters surgical implant into the body, or other applications intended to support or sustain life, ARCO Tower 15F or for any other application in which the failure of the Freescale Semiconductor product 1-8-1, Shimo-Meguro, Meguro-ku Tokyo 153-0064 could create a situation where personal injury or death may occur. Should Buyer...

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