Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 132

Memory Map
Offset
0x3_1010 ISR—Interrupt status register
0x3_1018 ICR—Interrupt clear register
0x3_1020 ID—Identification register
0x3_1028 EUASR—EU assignment status register
0x3_1030 MCR—Master control register
0x3_1108 CCCR—Crypto-channel configuration register
0x3_1110 CCPSR—Crypto-channel pointer status register
0x3_1140 CDPR—Crypto-channel current descriptor pointer register
0x3_1148 FF—Crypto-channel fetch FIFO address register
0x3_1180– DB n —Crypto-channel descriptor buffers [0–7]
0x3_11BF
0x3_1BF8 IP block revision register
0x3_2000 DEUMR—DEU mode register
0x3_2008 DEUKSR—DEU key size register
0x3_2010 DEUDSR—DEU data size register
0x3_2018 DEURCR—DEU reset control register
0x3_2028 DEUSR—DEU status register
0x3_2030 DEUISR—DEU interrupt status register
0x3_2038 DEUICR—DEU interrupt control register
0x3_2050 DEUEMR—DEU end-of-message register
0x3_2100 DEUIV—DEU initialization vector register
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
2-28
Table 2-2. Memory Map (continued)
Register
Channel
Data Encryption Standard Execution Unit (DEU)
Access Reset
R 0x0000_0000
_0000_0000
W 0x0000_0000
_0000_0000
R 0000_0000
_0000_00A0
R 0xF0F0_F0F0
_00FF_F0F0
R/W 0000_0000
_0000_0000
R/W 0x0000_0000
_0000_0000
R 0x0000_0000
_0000_0007
R 0x0000_0000
_0000_0000
W 0x0000_0000
_0000_0000
R 0x0000_0000
_0000_0000
R 0x0000_0000
_0002_00A0
R/W 0x0000_0000
_0000_0000
R/W 0x0000_0000
_0000_0000
R/W 0x0000_0000
_0000_0000
R/W 0x0000_0000
_0000_0000
R 0x0000_0000
_0000_0000
R 0x0000_0000
_0000_0000
R/W 0x0000_0000
_0000_3000
W 0x0000_0000
_0000_0000
R/W 0x0000_0000
_0000_0000
Freescale Semiconductor
Section/Page
14.6.4.3/14-70
14.6.4.4/14-71
14.6.4.5/14-73
14.6.4.1/14-67
14.6.4.7/14-74
14.5.1.1/14-55
14.5.1.2/14-57
14.5.1.3/14-62
14.5.1.4/14-62
14.5.1.5/14-63
14.6.4.6/14-73
14.4.1.1/14-19
14.4.1.2/14-20
14.4.1.3/14-21
14.4.1.4/14-22
14.4.1.5/14-23
14.4.1.6/14-24
14.4.1.7/14-25
14.4.1.8/14-27
14.4.1.9/14-27