Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 862

Enhanced Three-Speed Ethernet Controllers
15.6.2.1.1 Hardware Controlled Initialization
A hard reset occurs when the system powers up. All eTSEC's registers and control logic are reset to their
default states after a hard reset has occurred. In this state, each eTSEC behaves like a PowerQUICC II Pro
device, except for the absence of out-of-sequence TxBD features. That is, initially TCP/IP off-load is
disabled and only single RxBD and TxBD rings are accessible.
15.6.2.1.2 User Initialization
After the system has undergone a hard reset, software must initialize certain basic eTSEC registers. Other
registers can also be initialized during this time, but they are optional and must be determined based on the
requirements of the system. See
for register initialization.
After the initialization of registers is performed, the user must execute the following steps in the order
described below to bring the eTSEC into a functional state (out of reset):
1. Write to the MACCFG1 register and set the appropriate bits. These need to include RX_EN and
TX_EN. To enable flow control, Rx_Flow and Tx_Flow should also be set.
2. For the transmission of Ethernet frames, TxBDs must first be built in memory, linked together as
a ring, and pointed to by the TBASEn registers. A minimum of two buffer descriptors per ring is
required, unless the ring is disabled. Setting the ring to a size of one causes the same frame to be
transmitted twice. If TCP/IP off-load is to be enabled, the TxBD[TOE] bit must be set for each
frame.
3. Likewise, for the reception of Ethernet frames, the receive queue (or queues) must be ready, with
its RxBD pointed to by the RBASEn registers. If TCP/IP off-load is to be enabled,
RCTRL[PRSDEP] must be set to the required off-load level. Both transmit and receive can be
gracefully stopped after transmission and reception begins.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
15-144
Table 15-3 for the register list.
Table 15-143. Steps for Minimum Register Initialization
Description
1. Set and clear MACCFG1 [Soft_Reset]
2. Initialize MACCFG2
3. Initialize MAC station address
4. Set up the PHY using the MII Mgmt Interface
5. Configure the GMII
6. Clear IEVENT
7. Initialize IMASK
8. Initialize RCTRL
9. Initialize DMACTRL
Table 15-143 describes the minimum steps
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