Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 434

DDR Memory Controller
Table 9-31. DDR SDRAM Interface Timing Intervals (continued)
Timing Intervals
WRREC The number of clock cycles from the last beat of a write until a precharge command is allowed. This
interval, write recovery time, is listed in the AC specifications of the SDRAM as t
WRTORD Last write pair to read command. Controls the number of clock cycles from the last write data pair to the
subsequent read command to the same bank as t
The value of the above parameters (in whole clock cycles) must be set by boot code at system start-up (in
the TIMING_CFG_0, TIMING_CFG_1, TIMING_CFG_2, and TIMING_CFG_3 registers as described
in Section 9.4.1.4, "DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)," Section 9.4.1.5, "DDR
SDRAM Timing Configuration 1 (TIMING_CFG_1)," Section 9.4.1.6, "DDR SDRAM Timing
Configuration 2 (TIMING_CFG_2),"
(TIMING_CFG_3)") and be kept in the DDR memory controller configuration register space.
The following figures show SDRAM timing for various types of accesses. System software is responsible
(at reset) for optimally configuring SDRAM timing parameters. The programmable timing parameters
apply to both read and write timing configuration. The configuration process must be completed and the
DDR SDRAM initialized before any accesses to SDRAM are attempted.
Figure 9-23 through Figure 9-25
for a single-beat read operation,
burst-write operation. Note that all signal transitions occur on the rising edge of the memory bus clock and
that single-beat read operations are identical to burst-reads. These figures assume the CLK_ADJUST is
set to 1/2 DRAM cycle, an additive latency of 0 DRAM cycles is used, and the write latency is 1 DRAM
cycle (for DDR1).
SDRAM Clock
MCS
MRAS
MCAS
MA n
MWE
MDQ n
MDQS
Figure 9-23. DDR SDRAM Burst Read Timing—ACTTORW = 3, MCAS Latency = 2
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
9-40
and Section 9.4.1.3, "DDR SDRAM Timing Configuration 3
show DDR SDRAM timing for various types of accesses; see
Figure 9-24 for a single-beat write operation, and
0 1 2 3 4
ACTTORW
ROW COL
CASLAT
Definition
.
WTR
5 6 7 8
COL
D0 D1 D2 D3 D0 D1 D2 D3
.
WR
Figure 9-23
Figure 9-25 for a
9 10 11 12
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