Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 540

Enhanced Local Bus Controller
10.5.2.3 Read-Modify-Write Cycle for Parity Protected Memory Banks
Principally, a read-modify-write cycle is a read cycle immediately followed by a write cycle. Because the
write cycle will have a new address phase in any case, this basically is the same case as an address phase
after a previous read.
10.5.2.4 UPM Cycles with Additional Address Phases
The flexibility of the UPM allows the user to insert additional address phases during read cycles by
changing the AMX field, therefore turning around the bus during one pattern. The eLBC automatically
inserts a single bus turnaround cycle if the bus (LAD) was previously high impedance for any reason, such
as a read, before LALE is driven and LAD is driven with the new address. The turnaround cycle is not
inserted on a write, because the bus was already driven to begin with.
However, bus contention could potentially still occur on the far side of a bus transceiver. It is the
responsibility of the designer of the UPM pattern to guarantee that enough idle cycles are inserted in the
UPM pattern to avoid this.
10.5.3 Interface to Different Port-Size Devices
The eLBC supports 8- and 16-bit data port sizes. However, the bus requires that the portion of the data bus
used for a transfer to or from a particular port size be fixed. A 16-bit port must reside on LAD[0:15], and
an 8-bit port must reside on LAD[0:7]. The local bus always tries to transfer the maximum amount of data
on all bus cycles. Figure 10-74
0
OP0 OP1
LAD[0:7]
OP0 OP1
OP2 OP3
OP4 OP5
OP6 OP7
8-Bit Port Size
OP0
OP7
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
10-92
shows the device connections on the data bus.
OP2 OP3
LAD[8:15]
16-Bit Port Size
Figure 10-74. Interface to Different Port-Size Devices
Interface Output Register
31
OP4 OP5
63
OP6 OP7
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