Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 128

Memory Map
Offset
0x2_46A0 RPKT—Receive packet counter
0x2_46A4 RFCS—Receive FCS error counter
0x2_46A8 RMCA—Receive multicast packet counter
0x2_46AC RBCA—Receive broadcast packet counter
0x2_46B0 RXCF—Receive control frame packet counter
0x2_46B4 RXPF—Receive PAUSE frame packet counter
0x2_46B8 RXUO—Receive unknown OP code counter
0x2_46BC RALN—Receive alignment error counter
0x2_46C0 RFLR—Receive frame length error counter
0x2_46C4 RCDE—Receive code error counter
0x2_46C8 RCSE—Receive carrier sense error counter
0x2_46CC RUND—Receive undersize packet counter
0x2_46D0 ROVR—Receive oversize packet counter
0x2_46D4 RFRG—Receive fragments counter
0x2_46D8 RJBR—Receive jabber counter
0x2_46DC RDRP—Receive drop counter
0x2_46E0 TBYT—Transmit byte counter
0x2_46E4 TPKT—Transmit packet counter
0x2_46E8 TMCA—Transmit multicast packet counter
0x2_46EC TBCA—Transmit broadcast packet counter
0x2_46F0 TXPF—Transmit PAUSE control frame counter
0x2_46F4 TDFR—Transmit deferral packet counter
0x2_46F8 TEDF—Transmit excessive deferral packet counter
0x2_46FC TSCL—Transmit single collision packet counter
0x2_4700 TMCL—Transmit multiple collision packet counter
0x2_4704 TLCL—Transmit late collision packet counter
0x2_4708 TXCL—Transmit excessive collision packet counter
0x2_470C TNCL—Transmit total collision counter
0x2_4710 Reserved
0x2_4714 TDRP—Transmit drop frame counter
0x2_4718 TJBR—Transmit jabber frame counter
0x2_471C TFCS—Transmit FCS error counter
0x2_4720 TXCF—Transmit control frame counter
0x2_4724 TOVR—Transmit oversize frame counter
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
2-24
Table 2-2. Memory Map (continued)
Register
eTSEC Transmit Counters
Access Reset
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
— —
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
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