Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 971

Bits Name
0–27 — Reserved, should be cleared
28–29 pri_lvl1 Priority level for priority state 1.
30–31 pri_lvl0 Priority level for priority state 0.
16.3.2.27 System Interface Control Register (SI_CTRL)—Non-EHCI
Note that this register uses big-endian byte ordering and is not defined in the EHCI specification. The
system interface control register (SI_CTRL) controls various functions pertaining to the internal system
interface.
Offset 0x2_3410
0
R
W
Reset
Bits Name
0–26 —
27 err_disable
28–30 —
31 rd_prefetch_val Selects whether 32 bytes or 64 bytes are fetched during burst read transactions at the system
16.3.2.28 USB General Purpose Register (CONTROL)—Non-EHCI
Note that this register uses big-endian byte ordering and is not defined in the EHCI specification. The USB
general purpose (CONTROL) register contains the general-purpose IP control register outputs and is
shown in Figure 16-34.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 16-35. PRI_CTRL Register Field Descriptions
—
Figure 16-33. System Interface Control Register (SI_CTRL)
Table 16-36. SI_CTRL Register Field Descriptions
Reserved, should be cleared
When this bit is set, it causes the controller to ignore system bus errors. If cleared the controller
responds according to the values set in USBSTS[SEI] and USBINT[SEE].
0 enable
1 disable
Reserved, should be cleared
interface. When this input is LOW 64 bytes are fetched and when it is HIGH 32 bytes are fetched.
The setting of rd_prefetch_val must match the setting of the larger of TXPBURST and RXPBURST
fields in the BURSTSIZE register. If either of these fields is 64 bytes, then rd_prefetch_val must be
left cleared. Otherwise, this value should be set.
0 64-byte fetch
1 32-byte fetch
Description
26
disable
All zeros
Description
Universal Serial Bus Interface
Access: Read/Write
27 28 30
err_ rd_prefetch
—
31
_val
16-43