Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 124

Memory Map
Offset
0x2_4284 TMR_TXTS2_ID* - Tx timestamp identification tag (set 2)
0x2_4288– Reserved
0x2_42BC
0x2_42C0 TMR_TXTS1_H* - Tx timestamp high (set 1)
0x2_42C4 TMR_TXTS1_L* - Tx timestamp high (set 1)
0x2_42C8 TMR_TXTS2_H* - Tx timestamp high (set 2)
0x2_42CC TMR_TXTS2_L* - Tx timestamp high (set 2)
0x2_42D0– Reserved
0x2_42FC
0x2_4300 RCTRL—Receive control register
0x2_4304 RSTAT—Receive status register
0x2_4308– Reserved
0x2_430C
0x2_4310 RXIC—Receive interrupt coalescing register
0x2_4314 RQUEUE*—Receive queue control register.
0x2_4318– Reserved
0x2_432C
0x2_4330 RBIFX*—Receive bit field extract control register
0x2_4334 RQFAR*—Receive queue filing table address register
0x2_4338 RQFCR*—Receive queue filing table control register
0x2_433C RQFPR*—Receive queue filing table property register
0x2_4340 MRBLR—Maximum receive buffer length register
0x2_4344– Reserved
0x2_4380
0x2_4380 RBDBPH*—Rx data buffer pointer high bits
0x2_4384 RBPTR0—RxBD pointer for ring 0
0x2_4388 Reserved
0x2_438C RBPTR1*—RxBD pointer for ring 1
0x2_4390 Reserved
0x2_4394 RBPTR2*—RxBD pointer for ring 2
0x2_4398 Reserved
0x2_439C RBPTR3*—RxBD pointer for ring 3
0x2_43A0 Reserved
0x2_43A4 RBPTR4*—RxBD pointer for ring 4
0x2_43A8 Reserved
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
2-20
Table 2-2. Memory Map (continued)
Register
eTSEC Receive Control and Status Registers
Access Reset
R/W 0x0000_0000
— —
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
— —
R/W 0x0000_0000
w1c 0x0000_0000
— —
R/W 0x0000_0000
R/W 0x0080_0080
— —
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x nnnn_nnnn
R/W 0x nnnn_nnnn
R/W 0x0000_0000
— —
R/W 0x0000_0000
R/W 0x0000_0000
— —
R/W 0x0000_0000
— —
R/W 0x0000_0000
— —
R/W 0x0000_0000
— —
R/W 0x0000_0000
— —
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