Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 611

13.3.3.4 PCI Status Configuration Register
This register is used to record status information for PCI bus-related events. Some of the bits are
hard-wired to indicate the capabilities of the PCI controller. Other bits can be cleared by writing 1 to the
bit location. Figure 13-22
Offset 06
15 14
R DPERR SSERR RMA
W w1c w1c
Reset 0 0
Table 13-26 shows the bit settings of the PCI status register.
Table 13-26. PCI Status Configuration Register Field Descriptions
Bits Name
15 DPERR
14 SSERR
13 RMA
12 RTA
11 STA
10–9 DEVSEL_T DEVSEL timing. Hard-wired to 00.
8 DPD
7 FB-BC
6 —
5 66M
4 CL
3 INTS
2–0 —
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
shows the PCI status fields.
13 12 11 10
RTA STA DEVSEL_T
w1c w1c w1c
0 0 0 0
Figure 13-22. PCI Status Configuration Register
Detected parity error. Set whenever the PCI controller detects a parity error on the PCI bus, even
if parity error handling is disabled (as controlled by bit 6 in the PCI Command register).
Signaled system error. Set whenever PCI_SERR is asserted.
Received master abort. Set whenever the PCI controller, acting as the PCI master on the PCI bus,
terminates a transaction (except for a special-cycle) using master-abort.
Received target abort. Set whenever a transaction initiated by this PCI controller on the PCI bus is
terminated by a target-abort.
Signaled target abort. Set whenever the PCI controller, acting as the PCI target on the PCI bus,
issues a target-abort to a PCI master.
Master data parity error. Set when a data parity error is detected on the PCI bus, if the PCI controller
is the master that initiated the transaction and bit 6 in the PCI command register is set.
Fast back-to-back capable. Hard-wired to 1.
Reserved
66-MHz capable. Hard-wired to 1.
Capabilities list. Hard-wired to 1.
Interrupt status. Contains the status of the device interrupt. The value of this bit is not affected by
the INTD bit of the PCI command configuration register.
Reserved
9 8 7 6
DPD FB-BC
—
w1c
0 0 1 0
Description
PCI Bus Interface
Access: Mixed
5 4 3 2
66M CL INTS
w1c
1 1 0 0
0
—
0 0
13-29