Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 729

Table 15-2. eTSEC Signals—Detailed Signal Descriptions (continued)
Signal I/O
TSEC_1588_ALARM1 O
TSEC_1588_ALARM2 O
15.5 Memory Map/Register Definition
The eTSECs use a software model that is a superset of the PowerQUICC II Pro TSEC functionality and is
similar to that employed by the Fast Ethernet function supported on the Freescale MPC8260 CPM FCC
and in the FEC of the MPC860T.
The eTSEC device is programmed by a combination of control/status registers (CSRs) and buffer
descriptors. The CSRs are used for mode control, interrupts, and to extract status information. The
descriptors are used to pass data buffers and related buffer status or frame information between the
hardware and software.
All accesses to and from the registers must be made as 32-bit accesses. There is no support for accesses of
sizes other than 32 bits. Writes to reserved register bits must always store 0, as writing 1 to reserved bits
may have unintended side-effects. Reads from unmapped register addresses return zero. Unless otherwise
specified, the read value of reserved bits in mapped registers is not defined, and must not be assumed to
be 0.
This section of the document defines the memory map and describes the registers in detail. The buffer
descriptor is described in
15.5.1 Top-Level Module Memory Map
Each of the eTSECs is allocated 4 Kbytes of memory-mapped space. The space for each eTSEC is divided
as indicated in Table 15-3.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
1588 timer alarm 1. Timer current time is equal to or greater than alarm time comparator register.
User reprograms the TSEC_1588_ALARMn_H/L register to deactivate this output (chip external
output pin)
1588 timer alarm 2. Timer current time is equal to or greater than alarm time comparator register.
User reprograms the 1588_ALARMn_H/L register to deactivate this output (chip external output
pin)
Section 15.6.7, "Buffer Descriptors."
Table 15-3. Module Memory Map Summary
Address Offset
000–0FF eTSEC general control/status registers
100–2FF eTSEC transmit control/status registers
300–4FF eTSEC receive control/status registers
500–5FF MAC registers
600–7FF RMON MIB registers
800–8FF Hash table registers
900–9FF
A00–AFF FIFO control/status registers
B00–BFF DMA system registers
Enhanced Three-Speed Ethernet Controllers
Description
Function
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15-11