Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 306

Arbiter and Bus Monitor
Bits Name
26–27 APARK Address parking. Specifies arbiter bus parking mode.
00 Park to master. Arbiter parks the address bus to the master, that is selected by numeric value of
01 Park to last owner. Arbiter parks the address bus to last bus owner.
10 Disable. Arbiter does not assert BG to any master, if no BR is present.
11 Reserved
28–31 PARKM Parking master.
0000 e300 core
0001 PCI, DMA
0010 TSEC1, TSEC2
0011 Encryption core
0100 USB
0101–1111Reserved
6.2.2 Arbiter Timers Register (ATR)
The arbiter timers register (ATR) defines the arbiter address time out (ATO) and data time out (DTO)
values. Figure 6-2 shows the fields of ATR.
Offset 0x04
0
R
W
Reset 1 1 1 1 1
Table 6-3 describes ATR fields.
Bits Name
0–15 DTO Data time out. Specifies the time-out period for the data tenure. The granularity of this field is bus clocks. The
maximum value is coherent system bus clocks. Data time_out occurs if the data tenure does not end before
the specified time-out period. When DTO = n, the timeout cycle is n*128.
0000 Reserved
0001 128 clock cycles
0002 256 clock cycles
0003 384 clock cycles
...
FFFF 8355840 clock cycles
16–31 ATO Address time out. Specifies the time-out period for the address tenure. The granularity of this field is bus
clocks. Maximum value is coherent system bus clocks. Address time-out occurs if the address tenure did not
end before the specified time-out period. When ATO = n, the timeout cycle is n*128.
0000 Reserved
0001 128 clock cycles
0002 256 clock cycles
0003 384 clock cycles
...
FFFF 8355840 clock cycles
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
6-4
Table 6-2. ACR Field Descriptions (continued)
PARKM field.
DTO
1 1 1 1 1 1 1 1
Figure 6-2. Arbiter Timers Register (ATR)
Table 6-3. ATR Field Descriptions
Description
15 16
1 1 1 1 1 1 1 1
Description
Access: User read/write
ATO
1 1 1 1 1 1 1 1
Freescale Semiconductor
31
1 1 1