Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 341

Bits Name
25 DECAREN Decrementer auto reload
0 Normal operation.
1 Decrementer loads last mtdec value for precise periodic interrupt.
26 — Reserved, should be cleared.
27 FBIOB Force branch indirect on the bus
0 Register indirect branch targets are fetched normally
1 Forces register indirect branch targets to be fetched externally
28 ABE Address broadcast enable. Controls whether certain address-only operations (such as cache
operations) are broadcast on the bus.
0 Address-only operations affect only local caches and are not broadcast
1 Address-only operations are broadcast on the bus
Affected instructions are dcbi, dcbf, and dcbst. Note that these cache control instruction broadcasts
are not snooped by the e300 core. Refer to Section 4.3.3, "Data Cache Control," for more information.
29–30 — Reserved, should be cleared.
31 NOOPTI No-op the data cache touch instructions
0 The dcbt and dcbtst instructions are enabled
1 The dcbt and dcbtst instructions are no-oped internal to the e300 core
Table 7-3 shows how HID0[ECLK] and HID0[SBCLK] are used to configure the clk_out signal.
Table 7-3. Using HID0[ECLK] and HID0[SBCLK] to Configure clk_out
hreset
Asserted
Negated
Table 7-4 shows the bit definitions for HID1
Bits Name
0 PC0 PLL configuration bit 0 (read-only)
1 PC1 PLL configuration bit 1 (read-only)
2 PC2 PLL configuration bit 2 (read-only)
3 PC3 PLL configuration bit 3 (read-only)
4 PC4 PLL configuration bit 4 (read-only)
5 PC5 PLL configuration bit 5 (read-only)
6 PC6 PLL configuration bit 6 (read-only)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 7-2. e300 HID0 Bit Descriptions (continued)
ECLK SBCLK
x x Bus clock (small pulse for every rising edge of sysclk)
0 0 Clock output off
0 1 Core clock/2
1 0 Core clock
1 1 Bus clock
Table 7-4. HID1 Bit Descriptions
Function
clk_out
Description
e300 Processor Core Overview
7-23