Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 713

0
Field
Subfield
Reset
R/W
Addr
16
Field
Subfield
Reset
R/W
Addr
32
Field
Subfield
Reset
R/W
Addr
48
Field
Subfield
Reset
R/W
Addr
14.6.4.4 Interrupt Clear Register (ICR)
The interrupt control register (ICR) provides a means of clearing the ISR. When a bit in the ICR is written
with a 1, the corresponding bit in the ISR is cleared, clearing the interrupt output pin IRQ (assuming the
cleared bit in the ISR is the only interrupt source). If the input source to the ISR is a steady-state signal that
remains active, the appropriate ISR bit, and subsequently IRQ, will be reasserted shortly thereafter.
Figure 14-44 shows the bit positions of each interrupt source that can be cleared by this register. The
complete bit definitions for the ICR can be found in
Table 14-39.
When an ICR bit is written, it will automatically clear itself one cycle later. That is, it is not necessary to
write a '0' to a bit position which has been written with a '1'.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
19 20 21
— DONE Overflow
—
53
—
—
Figure 14-43. Interrupt Status Register (ISR)
—
—
0x0000
R
0x 3_1010
22 23 24
CH1
0x0000
R
0x 3_1010
—
—
0x0000
R
0x 3_1014
54 55 56 57 58
MDEU —
Err Dn — Err
0x0000
R
0x 3_1014
Figure 14-44. The bit fields are described in
Security Engine (SEC) 2.2
14
29 30
— CHN_1
— Err
59 60 62 62
AESU —
Dn — Err
15
ITO
31
Dn
47
63
DEU
Dn
14-71