Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 164

Signal Descriptions
Table 3-4. Output Signal States During System Reset (continued)
Interface
PCI_INTA
PCI_RESET_OUT
PCI_GNT[0:2]
UART_SOUT[0:1]
UART_RTS[0:1]
TSEC1_GTX_CLK
1
TSEC1_TXD[3:0]
TSEC1_TX_EN
TSEC2_GTX_CLK
TSEC2_TXD[3:0]
TSEC_MDC
LA[16:25]
LCS0
LCS1
LWE0/LFWE/LBS0
LWE1/LBS1
LBCTL
LALE
LOE/LGPL2/LFRE
LCLK[0:1]
USBDR_PCTL0
USBDR_PCTL1
MCP_OUT
TDO
QUIESCE
PCI_SYNC_OUT
USBDR_STP_SUSPEND
1
State of TSEC1_TXD0 depends on RTBI mode in TSEC1M bits in RCWH. Its state changes from 1 to 0 after RCWH is
loaded during reset sequence.
2
This pin should be pulled high during a hard reset for proper functionality of the device since it has a weak internal pull up.
No external pull-down resistors are allowed to be mounted on this net.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
3-30
Signal
PCI interrupt output
PCI reset output
PCI grant 0–2
DUART serial data out
DUART ready to send
eTSEC1 transmit clock out
eTSEC1 transmit data 2–0
eTSEC1 transmit enable
eTSEC2 transmit clock out
eTSEC2 transmit data 6-4
Ethernet management data clock
eLBC port address
eLBC chip select 0
eLBC chip select 1
eLBC write enable 0/FCM write enable
0/UPM byte (lane) select 0
eLBC write enable 1/UPM byte (lane)
select 1
eLBC data buffer control
eLBC address latch enable
eLBC output enable/GP line 2/FCM read
enable
eLBC clock
USB port control 0
USB port control 1
Machine check interrupt output
Test data out
Quiesce state
PCI sync output
2
USB host 0 data stop/suspend
State During Reset
'Z'
'0'
All 'Z'
All 'Z'
All 'Z'
'0'
All 'Z'
'0'
'Z'
All 'Z'
'0'
Active—used to load reset configuration word
Active—used to load reset configuration word
'1'
'1'
'1'
Active—used to load reset configuration word
Active—used to load reset configuration word
Active—used to load reset configuration word
All '0'
'1'
'0'
'Z'
'Z'
'1'
Active clock
Z
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