Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 750

Enhanced Three-Speed Ethernet Controllers
Bits Name
19 STEN MIB counter statistics enabled.
0 Statistics not enabled
1 Enables internal counters to update
This is a steady state signal and must be set prior to enabling the Ethernet controller and must not be
changed without proper care.
20–24 — Reserved
25 GMIIM GMII interface mode. If this bit is set, a PHY with a RGMII interface is expected to be connected. If
cleared, a PHY with an MII or RMII interface is expected. The user should then set MACCFG2[I/F Mode]
accordingly. The state of this status bit is defined during power-on reset.
0 MII or RMII mode interface expected
1 RGMII mode interface expected
27 RPM Reduced-pin mode for Gigabit interfaces. If this bit is set, a reduced-pin interface is expected on
Ethernet interfaces. RPM and RMM are never set together. This register can be pin-configured at reset
to 0 or 1.
0 MII in non-reduced-pin mode configuration
1 RGMII or RTBI reduced-pin mode
28 R100M RGMII/RMII 100 mode. This bit is ignored unless SGMIIM, RPM or RMM are set and MACCFG2[I/F
Mode] is assigned to 10/100 (01).
0 RGMII is in 10 Mbps mode;
SGMII is in 10 Mbps mode, and every 100th SGMII Reference clock is used to transfer data
1 RGMII is in 100 Mbps mode;
SGMII is in 100 Mbps mode, and every 10th SGMII Reference clock is used to transfer data
This bit must be cleared for 1-Gbps SGMII operation.
29 RMM Reduced-pin mode for 10/100 interfaces. If this bit is set, an RMII pin interface is expected. RMM must
be 0 if RPM = 1. This register can be pin-configured at reset to 0 or 1.
0 Non-RMII interface mode
1 RMII interface mode
30 SGMIIM Serial GMII mode. If this bit is set, a SGMII pin interface is expected to be connected via an on chip
SERDES.
This register can be pin-configured at reset to 0 or 1.
0 SGMII mode disabled. eTSEC connected via a parallel interface.
1 SGMII mode enabled.
31 — Reserved
The different interface configurations indicated by registers ECNTRL and MACCFG2 are summarized in
Table 15-12.
Interface Mode
RTBI 1Gbps
RGMII 1Gbps
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
15-32
Table 15-11. ECNTRL Field Descriptions (continued)
RMII is in 10 Mbps mode, and every 10th RMII Reference clock is used to transfer data
RMII is in 100 Mbps mode, and data is transferred on every Reference clock
Table 15-12. eTSEC Interface Configurations
1
FIFM GMIIM TBIM
0 0 1
0 1 0
Description
ECNTRL Field
RPM R100M RMM
1 — —
1 — —
MACCFG2 Field
SGMIIM I/F Mode
0 10
0 10
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