Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 254

System Configuration
Table 5-49 defines the bit fields of PTCNR.
Bits Name
0–23 — Write reserved, read = 0
24 CLEN Clock enable control bit. Controls the counting of the PIT. When the PIT's clock is disabled, the counter
maintains its old value. When the counter's clock is enabled, it continues counting using the previous value.
0 Disable counter.
1 Enable counter.
25 CLIN Input clock control bit. The input clock to the PIT can be either an internal system clock or an external PIT
clock.
0 The input clock to the periodic interrupt timer is internal system clock.
1 The input clock to the periodic interrupt timer is external PIT clock.
26–30 — Write reserved, read = 0
31 PIM Periodic interrupt mask bit. Used to enable or disable (mask) the PIT periodic interrupt.
0 Periodic interrupt generation disabled.
1 Periodic interrupt generation enabled.
5.6.5.2 Periodic Interval Timer Load Register (PTLDR)
The periodic interval timer load register (PTLDR), shown in
loaded in a 32-bit PIT counter.
Offset 0x04
0
R
W
Reset
Table 5-50 defines the bit fields of PTLDR.
Bits Name
0–31 CLDV Contains the 32-bit value to be loaded in a 32-bit PIT counter.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
5-46
Table 5-49. PTCNR Bit Settings
Figure 5-34. Periodic Interval Timer Load Register (PTLDR)
Table 5-50. PTLDR Bit Settings
Description
Figure 5-34, contains the 32-bit value to be
CLDV
All zeros
Description
Access: Read/Write
31
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