Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 791

MIIM registers for that eTSEC. For example, if a RTBI interface is required on eTSEC2, then the MIIM
registers starting at offset 0x2_5520 are used to configure it.
Figure 15-41 describes the definition for the MIIMCFG register.
Offset eTSEC1:0x2_4520
0
R
Reset Mgmt
W
Reset 0
Figure 15-41. MII Management Configuration Register Definition
Table 15-45 describes the fields of the MIIMCFG register.
Bits Name
0 Reset Mgmt Reset management. This bit is cleared by default.
0 Allow the MII MGMT to perform mgmt read/write cycles if requested through the host interface.
1 Reset the MII MGMT.
1–26 — Reserved
27 No Pre Preamble suppress. This bit is cleared by default.
0 The MII MGMT performs Mgmt read/write cycles with 32 clocks of preamble.
1 The MII MGMT suppresses preamble generation and reduces the Mgmt cycle from 64 clocks to 32
clocks. This is in accordance with IEEE 802.3/22.2.4.4.2.
28 — Reserved
29–31 MgmtClk This field determines the clock frequency of the MII management clock (EC_MDC). Its default value is
111.
Note: The eTSEC system clock is derived from (CCB Clock)/2.
000 1/4 of the eTSEC system clock divided by 8
001 1/4 of the eTSEC system clock divided by 8
010 1/6 of the eTSEC system clock divided by 8
011 1/8 of the eTSEC system clock divided by 8
100 1/10 of the eTSEC system clock divided by 8
101 1/14 of the eTSEC system clock divided by 8
110 1/20 of the eTSEC system clock divided by 8
111 1/28 of the eTSEC system clock divided by 8
15.5.3.5.7 MII Management Command Register (MIIMCOM)
The MIIMCOM register is written by the user.
Offset eTSEC1:0x2_4524
0
R
W
Reset
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 15-45. MIIMCFG Field Descriptions
—
Figure 15-42. MIIMCOM Register Definition
—
Description
Figure 15-42 describes the definition for MIIMCOM.
All zeros
Enhanced Three-Speed Ethernet Controllers
Access: Read/Write
26 27
No Pre — MgmtClk
0 0
Access: Read/Write
29 30
Scan Cycle
28 29 31
0 1 1 1
31
Read Cycle
15-73