Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 817

15.5.3.6.40 Transmit Control Frame Counter (TXCF)
Figure 15-91 describes the definition for the TXCF register.
Offset eTSEC1:0x2_4720; eTSEC2:0x2_5720
0
R
W
Reset
Figure 15-91. Transmit Control Frame Counter Register Definition
Table 15-95 describes the fields of the TXCF register.
Bits Name
0–19 — Reserved
20–31 TXCF Transmit control frame counter. Increments for every control frame with valid CRC and of lengths
64 to 1518 (non VLAN) or 1522 (VLAN).
15.5.3.6.41 Transmit Oversize Frame Counter (TOVR)
Figure 15-92 describes the definition for the TOVR register.
Offset eTSEC1:0x2_4724; eTSEC2:0x2_5724
0
R
W
Reset
Figure 15-92. Transmit Oversized Frame Counter Register Definition
Table 15-96 describes the fields of the TOVR register.
Bits Name
0–19 — Reserved
20–31 TOVR Transmit oversize frame counter. Increments for each oversized transmitted frame with a correct
FCS value.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
—
All zeros
Table 15-95. TXCF Field Descriptions
Description
—
All zeros
Table 15-96. TOVR Field Descriptions
Description
Enhanced Three-Speed Ethernet Controllers
Access: Read/Write
19 20
TXCF
Access: Read/Write
19 20
TOVR
31
31
15-99