Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 538

Enhanced Local Bus Controller
Local Bus Interface
Figure 10-71. Local Bus Peripheral Hierarchy for High Bus Speeds
10.5.1.5 GPCM Timings
In case a system contains a memory hierarchy with high speed synchronous memories (synchronous
SRAM) and lower speed asynchronous memories (for example, FLASH EPROM and peripherals) the
GPCM-controlled memories should be decoupled by buffers to reduce capacitive loading on the bus.
Those buffers have to be taken into account for the timing calculations.
Local Bus Interface
To calculate address setup timing for a slower peripheral/memory device, several parameters have to be
added: propagation delay for the address latch, propagation delay for the buffer and the address setup for
the actual peripheral. Typical values for the two propagation delays are in the order of 3–6 ns, so for a
133-MHz bus frequency, LCS should arrive on the order of 3 bus clocks later.
For data timings, only the propagation delay of one buffer plus the actual data setup time has to be
considered.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
10-90
LA n
LAD n
A/D
LALE
LE
LBCTL
DIR
Muxed Address/Data
Unmuxed Address
Buffered Data
LAD[0:15]
Latch
LALE
LBCTL
Figure 10-72. GPCM Address Timings
MA
Latch
Q
A
B DQ
A
Buffer A
Muxed Address/Data
Unmuxed Address
Buffered Address
SSRAM
A
DQ
Slower
Memories
and
Peripherals
Slower
Device
Memories
Input
and
Pin
Peripherals
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