Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 223

These other mapping functions are configured by programming the configuration, control, and status
registers of the individual interfaces. Note that there is no need to have a one-to-one correspondence
between local access windows and chip select regions or outbound windows. A single local access window
can be further decoded to any number of chip selects or to any number or outbound windows at the target
interface.
5.2.8 Outbound Address Translation and Mapping Windows
Outbound address translation and mapping refers to the translation of addresses from the local 32-bit
address space to the external address space and attributes of a particular I/O interface. On this device, the
PCI block has an outbound address translation unit.
The PCI controller has six outbound windows plus a default window. See
Map/Register Definitions,"
5.2.9 Inbound Address Translation and Mapping Windows
Inbound address translation and mapping refers to the translation of an address from the external address
space of an I/O interface (such as PCI address space) to the local address space understood by the internal
interfaces of this processor. It also refers to the mapping of transactions to a particular target interface and
the assignment of transaction attributes. The PCI controller has inbound address translation unit.
5.2.9.1 PCI Inbound Windows
The PCI controller has three general inbound windows plus a dedicated window for memory mapped
configuration accesses (PIMMR). These windows have a one-to-one correspondence with the base address
registers in the PCI programming model. Updating one automatically updates the other. There is no default
inbound window; if a PCI address does not match one of the inbound windows, this processor does not
respond with an assertion of PCI_DEVSEL. See
a detailed description of the PCI inbound windows.
5.2.10 Internal Memory Map
All of the memory mapped configuration, control, and status registers in the device are contained within
a 1-Mbyte address region, referred as the IMMR. To allow for flexibility, the internal memory map block
can be relocated in the local address space. The local address map location of this register block is
controlled by the internal memory map registers' base address register (IMMRBAR); see
"Internal Memory Map Registers Base Address Register (IMMRBAR)."
IMMRBAR is 0xFF40_0000.
The internal memory map window is always the highest priority local access
window.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
for a detailed description of the PCI outbound windows.
Section 13.4.6, "PCI Inbound Address Translation,"
NOTE
System Configuration
Section 4.5, "Memory
Section 5.2.4.1,
The default value for the
for
5-15