Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 805

15.5.3.6.16 Receive Alignment Error Counter (RALN)
Figure 15-67 describes the definition for the RALN register.
Offset eTSEC1:0x2_46BC; eTSEC2:0x2_56BC
0
R
W
Reset
Figure 15-67. Receive Alignment Error Counter Register Definition
Table 15-71 describes the fields of the RALN register.
Bits Name
0–15 — Reserved
16–31 RALN Receive alignment error counter. Increments for each received frame from 64 to 1518 (non VLAN) or 1522
(VLAN) which contains an invalid FCS and is not an integral number of bytes.
15.5.3.6.17 Receive Frame Length Error Counter (RFLR)
Figure 15-68 describes the definition for the RFLR register.
Offset eTSEC1:0x2_46C0; eTSEC2:0x2_56C0
0
R
W
Reset
Figure 15-68. Receive Frame Length Error Counter Register Definition
Table 15-72 describes the fields of the RFLR register.
Bits Name
0–15 — Reserved
16–31 RFLR Receive frame length error counter. Increments for each frame received in which the 802.3 length field did
not match the number of data bytes actually received (46–1500 bytes). The counter does not increment if
the length field is not a valid 802.3 length, such as an Ethertype value.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
—
All zeros
Table 15-71. RALN Field Descriptions
—
All zeros
Table 15-72. RFLR Field Descriptions
Enhanced Three-Speed Ethernet Controllers
15 16
Description
15 16
Description
Access: Read/Write
RALN
Access: Read/Write
RFLR
15-87
31
31