Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 771

Bits Name
3–10 ICFT Interrupt coalescing frame count threshold. While interrupt coalescing is enabled (RXIC[ICE] is set), this value
determines how many frames are received before raising an interrupt. The eTSEC threshold counter is reset
to ICFT following an interrupt. The value of ICFT must be greater than zero avoid unpredictable behavior.
11–15 — Reserved
16–31 ICTT Interrupt coalescing timer threshold. While interrupt coalescing is enabled (RXIC[ICE] is set), this value
determines the maximum amount of time after receiving a frame before raising an interrupt. If frames have
been received but the frame count threshold has not been met, an interrupt is raised when the threshold timer
reaches zero. The threshold timer is reset to the value in this field and begins counting down upon receiving
the first frame having its RxBD[I] bit set. The threshold value is represented in units equal to 64 periods of the
clock specified by RXIC[ICCS]. ICTT must be greater than zero to avoid unpredictable behavior.
15.5.3.3.4 Receive Queue Control Register (RQUEUE)
The RQUEUE register enables each of the RxBD rings 0–7. By default, RxBD ring 0 is enabled.
Figure 15-25 describes the definition for the RQUEUE register.
Offset eTSEC1:0x2_4314; eTSEC2:0x2_5314
0
R
W
Reset
0 0 0 0 0 0 0 0
Table 15-30 describes the RQUEUE register.
\
Bits Name
0–23 — Reserved
24 EN0 Receive queue 0 enable.
0 RxBD ring is not queried for reception. In effect the receive queue is disabled.
1 RxBD ring is queried for reception.
25 EN1 Receive queue 1 enable.
0 RxBD ring is not queried for reception. In effect the receive queue is disabled.
1 RxBD ring is queried for reception.
26 EN2 Receive queue 2 enable.
0 RxBD ring is not queried for reception. In effect the receive queue is disabled.
1 RxBD ring is queried for reception.
27 EN3 Receive queue 3 enable.
0 RxBD ring is not queried for reception. In effect the receive queue is disabled.
1 RxBD ring is queried for reception.
28 EN4 Receive queue 4 enable.
0 RxBD ring is not queried for reception. In effect the receive queue is disabled.
1 RxBD ring is queried for reception.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 15-29. RXIC Field Descriptions (continued)
—
1 0 0 0 0 0
Figure 15-25. RQUEUE Register Definition
Table 15-30. RQUEUE Field Descriptions
Enhanced Three-Speed Ethernet Controllers
Description
23
0 0 0 0 0 0 0 0 0 0
Description
Access: Read/Write
24 25 26 27 28 29
EN0 EN1 EN2 EN3 EN4 EN5 EN6 EN7
1 0 0 0 0 0
30 31
0 0
15-53