Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 779

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PID Bit Name
1011 0–23 — Reserved, should be written with zero.
24–31 L4P Layer 4 protocol identifier as per published IANA specification. This is the last recognized protocol type
recognized in the case of IPv6 extension headers. This value defaults to 0xFF to indicate that no layer
4 header was recognized (possibly due to absence of an IP header).
1100 0–31 DIA Destination IP address. If an IPv4 header was found, this is the entire destination address. If an IPv6
header was found, this is the 32 most significant bits of the 128-bit destination address. This value
defaults to 0x0000_0000 if no IP header appeared.
1101 0–31 SIA Source IP address. If an IPv4 header was found, this is the entire source address. If an IPv6 header was
found, this is the 32 most significant bits of the 128-bit source address. This value defaults to
0x0000_0000 if no IP header appeared.
1110 0–15 — Reserved, should be written with zero.
16–31 DPT Destination port number for TCP or UDP headers. This value defaults to 0x0000 if no TCP or UDP
headers were recognized.
1111 0–15 — Reserved, should be written with zero.
16–31 SPT Source port number for TCP or UDP headers. This value defaults to 0x0000 if no TCP or UDP headers
were recognized.
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PID is the property identifier field of the filer table control entry (see RQFCR[PID]) at the same index.
15.5.3.3.9 Maximum Receive Buffer Length Register (MRBLR)
The MRBLR register is written by the user. It informs the eTSEC how much space is in the receive buffer
pointed to by the RxBD.
Offset eTSEC1:0x2_4340; eTSEC2:0x2_5340
0
R
W
Reset
\\
Bits Name
0–15 — Reserved
16–25 MRBL Maximum receive buffer length. MRBL is the number of bytes that the eTSEC receiver writes to the receive
buffer. The MRBL register is written by the user with a multiple of 64 for all modes. The eTSEC can write fewer
bytes to the buffer than the value set in MRBL if a condition such as an error or end-of-frame occurs, but it
never exceeds the MRBL value; therefore, user-supplied buffers must be at least as large as the MRBL. MRBL
must be set, together with the number of buffer descriptors, to ensure adequate space for received frames.
See Section 15.5.3.5.5, "Maximum Frame Length Register
26–31 — To ensure that MRBL is a multiple of 64, these bits are reserved and should be cleared.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 15-34. RQFPR Field Descriptions (continued)
Figure 15-31 describes the definition for the MRBLR.
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Figure 15-31. MRBLR Register Definition
Table 15-35. MRBLR Field Descriptions
Enhanced Three-Speed Ethernet Controllers
Description
15 16
MRBL
All zeros
Description
(MAXFRM)," for further discussion.
Access: Read/Write
25 26 31
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15-61