Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 163

3
The LB_POR_CFG_BOOT_ECC_DIS function will be selected on the TSEC_MDC pin whenever HRESET is
asserted; the pin will act as TSEC_MDC at all other times. The reset block will sample this signal on PORESET
negation only; the sampled value is then passed to the eLBC controller to enable/disable ECC checking during boot
time. An internal pull-down resistor has been added to this pad to enable the boot-time ECC checking by default. A
pull-up resistor, via a three-state buffer, is needed during HRESET assertion period to disable ECC checking during
boot time.
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Must be connected to a 10K ±1% precision resistor if using the integrated USB PHY through the UTMI.
3.2 Configuration Signals Sampled at Reset
The signals that serve alternate functions as configuration input signals during system reset are
summarized in Table 3-3. The detailed interpretation of their voltage levels during reset is described in
Chapter 4, "Reset, Clocking, and Initialization."
Dedicated pin
Dedicated pin
3.3 Output Signal States During Reset
When a system reset is recognized (PORESET or HRESET are asserted), the device aborts all current
internal and external transactions and releases all bidirectional I/O signals to a high-impedance state. See
Chapter 4, "Reset, Clocking, and Initialization,"
During reset, the device ignores most input signals (except for the reset configuration signals) and drives
most of the output-only signals to an inactive state.
Interface
MDM[0:3]
MBA[0:2]
MA[0:14]
MWE
MRAS
MCAS
MCS[0:1]
MCKE
MCK
MCK
MODT[0:1]
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 3-3. Reset Configuration Signals
Functional
Functional Signal Name
Interface
eTSEC2 TSEC2_TXD[3:0]
None (dedicated pin)
None (dedicated pin)
Table 3-4. Output Signal States During System Reset
Signal
DDR data mask
DDR bank select
DDR address
DDR write enable
DDR row address strobe
DDR column address strobe
DDR chip select (2/DIMM)
DDR clock enable
DDR differential clocks
DDR differential clocks
DRAM on-die termination
Reset Configuration Name
CFG_RESET_SOURCE[0:3]
CFG_CLKIN_DIV
CFG_LBIU_MUX_EN
for a complete description of the reset functionality.
Table 3-4 shows the states of the output-only signals.
Signal Descriptions
State During Reset
All 'Z'
All 'Z'
All 'Z'
'Z'
'Z
'Z'
Both 'Z'
'0'
'0'
'1'
Both '0'
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