Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 745

Bits Name
21 MMRD MII management read completion
0 MII management read not issued or in process.
1 MII management read completed that was initiated by a user through the MII Scan or Read cycle
command.
22 MMWR MII management write completion
0 MII management write not issued or in process.
1 MII management write completed that was initiated by a user write to the MIIMCON register.
23 GRSC Graceful receive stop complete. This interrupt is asserted if a graceful receive stop is completed. It allows
the user to know if the system has completed the stop and it is safe to write to receive registers (status,
control or configuration registers) that are used by the system during normal operation.
0 Graceful stop not completed.
1 Graceful stop completed.
24 RXF Receive frame interrupt. This bit indicates that a frame was received and the last receive buffer descriptor
(RxBD) in that frame was updated. This occurs either if the I (interrupt) bit in the buffer descriptor status word
is set, or an overrun error occurs. The specific receive queue that was updated has its RXF bit set in RSTAT.
0 Frame not received.
1 Frame received.
25–26 — Reserved
27 FGPI Filer generated general purpose interrupt on a set of filer rule match. This bit will be set upon reception of
a frame that matches a GPI rule sequence that is specified in the filer. It is synchronized with the setting of
RXF.
0 No filer generated interrupt has occurred.
1 The filer has accepted a frame via a matching rule that the RQFCR[GPI] bit set.
28 FIR The receive queue filer result is invalid, either because not enough time between frames was available to
find a matching rule, or no entry in the filer table could be matched.
0 Receive queue filer reached a definite result; however, bit FIQ may still be set if a frame was filed to a
disabled RxBD ring.
1 Receive queue filer was unable to reach a definite result. In this case, bit FIQ is also set if no entry in the
filer table could provide a rule match.
29 FIQ Filed frame to invalid receive queue. This bit indicates that either the receive queue filer chose to DMA a
received frame to a disabled RxBD ring, or that no rule in the filer table could be matched.
0 Received frames filed to valid queues or rejected. Note that a frame may be rejected if the filer has
insufficient time to reach a conclusive result between frames, in which case bit FIR is set.
1 Received frames filed to RxBD rings that are not enabled. The frame is discarded. If bit FIR is also set
this indicates that the filer exhausted all of its table entries without a rule match.
30 DPE Internal data parity error. This bit indicates that the eTSEC has detected a parity error on its stored data,
which is likely to compromise the validity of recently transferred frames.
0 No parity errors detected.
1 Data held in the FIFO or filer arrays is expected to be corrupted due to a parity error.
31 PERR Receive frame parse error for TCP/IP off-load. This bit indicates that a received frame could not be parsed
unambiguously, due to encapsulated header type fields contradicting each other.
0 Received frame parsed successfully.
1 Received frame parse revealed header inconsistencies.
15.5.3.1.4 Interrupt Mask Register (IMASK)
The interrupt mask register provides control over which possible interrupt events in the IEVENT register
are permitted to participate in generating hardware interrupts to the PIC. All implemented bits in this
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 15-8. IEVENT Field Descriptions (continued)
Enhanced Three-Speed Ethernet Controllers
Description
15-27