Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 92

Overview
Filing can be based on Ethernet, IP, and TCP/UDP properties, including VLAN fields, Ether-type, IP
protocol type, IP TOS or differentiated services, IP source and destination addresses, TCP/UDP port
numbers, or user-defined bit fields.
Each eTSEC provides a full-duplex packet FIFO interface port that bypasses the Ethernet MAC but reuses
the PHY interface pins. As a result, the FIFO interface normally does not impose the overheads of Ethernet
framing. The FIFO interface operates synchronously, at up to 200MHz, providing up to 3.2-Gbps
full-duplex transfer rates. Bare IP packets, with an optional 32-bit CRC check sequence, can be transferred
to the eTSEC directly. The eTSEC Tx and Rx FIFOs, TCP/IP acceleration functions, and DMA continue
to be used in packet FIFO mode.
While some of the Ethernet interfaces support either 2.5- or 3.3-V operation,
the voltages of eTSEC1 and eTSEC2 must be the same.
Table 1-1 lists available configurations.
Mode Option
Ethernet standard interfaces
Ethernet reduced interfaces
FIFO and mixed interfaces
1
Both interfaces must use the same voltage.
1.2.5 PCI Controller
The 32-bit PCI controller is compatible with the PCI Local Bus Specification, Rev. 2.3. The PCI interface
can function as a host bridge interface. The PCI interface can optionally function as an agent device. The
PCI controller supports 32-bit addressing and 32-bit data buses.
As a host, the device supports read and write operations to the PCI memory space, the PCI I/O space, and
the PCI configuration space. Also, the device can generate PCI special-cycle and interrupt acknowledge
commands. As an agent, the device supports read and write operations to system memory, as well as PCI
configuration space and the on-chip memory mapped configuration space.
The device PCI controller includes the following distinctive features:
• Address stepping on configuration transactions
• Fast back-to-back transactions
• Data streaming
• When in host mode, the PCI controller supports external signal isolation, thus enabling power shut
off to external devices
• Supports PCI Power Management 1.2
• Supports PME generation (agent) and Wake on PME
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
1-12
Table 1-1. Supported eTSEC1 and eTSEC2 Configurations
eTSEC1
TBI, GMII, or MII
RTBI, RGMII, or RMII
8-bit FIFO
TBI, GMII, MII, RTBI, RGMII,
RMII, or 8-bit FIFO
NOTE
TBI, GMII, or MII
RTBI, RGMII, or RMII
RTBI, RGMII, RMII, or 8-bit FIFO
1
eTSEC2
8-bit FIFO
Freescale Semiconductor