Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 122

Memory Map
Offset
0x2_3408 AGE_CNT_THRESH—Age count threshold
0x2_340C PRI_CTRL—Priority control
0x2_3410 SI_CTRL—System interface control
0x2_3500 CONTROL—Control
0x2_3504– Reserved, should be cleared
0x2_3FFF
0x2_4000 TSEC_ID*—Controller ID register
0x2_4004 TSEC_ID2*—Controller ID register
0x2_4008– Reserved
0x2_400C
0x2_4010 IEVENT—Interrupt event register
0x2_4014 IMASK—Interrupt mask register
0x2_4018 EDIS—Error disabled register
0x2_401C Reserved
0x2_4020 ECNTRL—Ethernet control register
0x2_4024 Reserved
0x2_4028 PTV—Pause time value register
0x2_402C DMACTRL—DMA control register
0x2_4030 Reserved
0x2_4034– Reserved
0x2_40FC
0x2_4100 TCTRL—Transmit control register
0x2_4104 TSTAT—Transmit status register
0x2_4108 DFVLAN*—Default VLAN control word
0x2_410C Reserved
0x2_4110 TXIC—Transmit interrupt coalescing register
0x2_4114 TQUEUE*—Transmit queue control register
0x2_4118– Reserved
0x2_413C
0x2_4140 TR03WT*—TxBD Rings 0–3 round-robin weightings
0x2_4144 TR47WT*—TxBD Rings 4–7 round-robin weightings
0x2_4148– Reserved
0x2_4180
0x2_4180 TBDBPH*—Tx data buffer pointer high bits
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
2-18
Table 2-2. Memory Map (continued)
Register
eTSEC General Control and Status Registers
eTSEC Transmit Control and Status Registers
Access Reset
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
Mixed 0x0000_0000
— —
R 0x0124_0106
R 0x0030_00F0
— —
w1c 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
— —
R/W 0x0000_0000
— —
R/W 0x0000_0000
R/W 0x0000_0000
— —
— —
R/W 0x0000_0000
w1c 0x0000_0000
R/W 0x8100_0000
— —
R/W 0x0000_0000
R/W 0x0000_8000
— —
R/W 0x0000_0000
R/W 0x0000_0000
— —
R/W 0x0000_0000
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