Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 752

Enhanced Three-Speed Ethernet Controllers
15.5.3.1.8 DMA Control Register (DMACTRL)
DMACTRL is writable by the user to configure the DMA block.
the DMACTRL register.
Offset eTSEC1:0x2_402C; eTSEC2:0x2_502C
0
R
W
Reset
Table 15-14 describes the fields of the DMACTRL register.
Bits Name
0–15 — Reserved
16 LE Little-endian descriptor mode enable. This bit controls both the reading and writing of descriptors; data
buffers are always transferred in network byte order.
0 RxBDs and TxBDs are interpreted with big-endian byte ordering, as shown in
Buffer Descriptors."
1 RxBDs and TxBDs are interpreted with little-endian byte ordering. That is, the 16 bits of flags are
considered a complete half-word unit, the buffer length is considered another complete half-word unit, and
the buffer pointer is considered a complete word unit.
17–23 — Reserved
24 TDSEN Tx Data snoop enable.
0 Disables snooping of all transmit frames from memory.
1 Enables snooping of all transmit frames from memory.
25 TBDSEN TxBD snoop enable.
0 Disables snooping of all transmit BD memory accesses.
1 Enables snooping of all transmit BD memory accesses.
26 — Reserved
27 GRS Graceful receive stop. If this bit is set, the Ethernet controller stops receiving frames following completion of
the frame currently being received. (That is, after a valid end of frame was received). The contents of the Rx
FIFO are then written to memory, and the IEVENT[GRSC] is set to indicate that all current receive buffers
have been closed. Because the receive enable bit of the MAC may still be set, the MAC may continue to
receive but the eTSEC ignores the receive data until GRS is cleared. If this bit is cleared, the eTSEC scans
the input data stream for the start of a new frame (preamble sequence and start of frame delimiter) and the
first valid frame received uses the next RxBD.
If GRS is set, the user must monitor the graceful receive stop complete (GRSC) bit in the IEVENT register to
insure that the graceful receive stop was completed. The user can then clear IEVENT[GRSC] and can write
to receive registers that are accessible to both user and the eTSEC hardware without fear of conflict.
0 eTSEC scans input data stream for valid frame.
1 eTSEC stops receiving frames following completion of current frame.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
15-34
15 16 17
— LE
Figure 15-9. DMACTRL Register
Table 15-14. DMACTRL Field Descriptions
Figure 15-9
23 24 25
— TDSEN TBDSEN — GRS GTS TOD WWR WOP
All zeros
Description
describes the definition for
Access: Read/Write
26 27 28 29 30
Section 15.6.7.1, "Data
Freescale Semiconductor
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