Bits
Name
58
HALT
Halt. Indicates that the AESU has halted due to an error.
0 AESU not halted
1 AESU halted
Note: Because the error causing the AESU to stop operating may be masked before reaching the interrupt
status register, the AESU interrupt status register (AESUISR) is used to provide a second source of
information regarding errors preventing normal operation.
59–60
ICR
Integrity check result
00 No integrity check was performed.
01 The integrity check passed.
10 The integrity check failed.
11 Reserved
61
IE
Interrupt error. This status bit reflects the state of the ERROR interrupt signal, as sampled by the controller
interrupt status register
0 AESU is not signaling error
1 AESU is signaling error
62
ID
Interrupt done. This status bit reflects the state of the DONE interrupt signal, as sampled by the controller
interrupt status register
0 AESU is not signaling done
1 AESU is signaling done
63
RD
Reset done. This status bit, when high, indicates that AESU has completed its reset sequence, as reflected
in the signal sampled by the channel.
0 Reset in progress
1 Reset done
Note: Reset done resets to 0, but has typically switched to 1 by the time a user checks the register, indicating
the EU is ready for operation.
14.4.3.6
AESU Interrupt Status Register (AESUISR)
The AESU interrupt status register (AESUISR), shown in
if those errors are not masked, through the AESU interrupt control register (AESUICR).
0
Field
—
Reset
R/W
Addr
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 14-28. AESUSR Field Descriptions (continued)
(Section 14.6.4.3, "Interrupt Status Register
(Section 14.6.4.3, "Interrupt Status Register
48
49
50
51
ICE
—
IE
ERE CE KSE DSE ME AE OFE IFE IFU IFO OFU —
Figure 14-31. AESU Interrupt Status Register (AESUISR)
Description
Figure
14-31, tracks the state of possible errors,
52
53
54
55
56
0
R
AESU 0x3_4030
Security Engine (SEC) 2.2
(ISR)").
(ISR)").
57
58
59
60
61
62
63
14-45