Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 842

Enhanced Three-Speed Ethernet Controllers
Offset
Address
0x08 AN link partner ability next page
(ANLPANP)
0x0F Extended status (EXST)
0x10 Jitter diagnostics (JD)
0x11 TBI control (TBICON)
1
R = Read-only, WO = Write Only, R/W = Read and Write, LH = Latches High, LL = Latches Low,
SC = Self-clearing,
15.5.4.3.1 Control Register (CR)
Figure 15-117 describes the definition for the CR register.
Offset 0x00
0 1 2
R PHY
— Speed[0] AN Enable
Reset
W
Reset 0 0 0
Table 15-126 describes the fields of the CR register.
Bits Name
0 PHY Reset PHY reset. This bit is cleared by default. This bit is self-clearing.
0 Normal operation.
1 The internal state of the TBI is reset. This in turn may change the state of the TBI link partner.
1 — Reserved
2 Speed[0] Speed selection. This bit defaults to a cleared state and should always be cleared, which corresponds to
1000 Mbps speed.Setting this field controls the speed at which the TBI operates. The table for Speed[1]
provides the appropriate encoding. Its default is bit[2] = '0'; bit[9] = '1'.
3 AN Auto-negotiation enable. This bit is set by default.
Enable 0 The values programmed in bits 2, 7 and 9 determine the operating condition of the link.
1 Auto-negotiation process enabled.
4–5 — Reserved
6 Reset AN Reset auto-negotiation. This bit is cleared by default and is self-clearing.
0 Normal operation.
1 The auto-negotiation process restarts. This action is only available if auto-negotiation is enabled.
7 Full Duplex mode. This bit is set by default.
Duplex 0 Reserved.
1 Full-duplex operation.
8 — Reserved, should be cleared.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
15-124
Table 15-125. TBI MII Register Set (continued)
Name
3 4 5 6
— Reset AN Full Duplex — Speed[1]
1 0 0 0
Figure 15-117. Control Register Definition
Table 15-126. CR Field Descriptions
Access Size
R 16 bits
R 16 bits
R/W 16 bits
R/W 16 bits
7 8 9 10
1 0 1 0
Description
Section/page
15.5.4.3.7/15-130
15.5.4.3.8/15-131
15.5.4.3.9/15-132
15.5.4.3.10/15-133
Access: Read/Write
15
—
0 0 0 0 0
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