Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 972

Universal Serial Bus Interface
Offset 0x2_3500
0
R
W
Reset
16 18 19 20
R
CLKIN_
—
SEL
W
Reset
Bits Name
0–13 —
14 PHY_CLK_
VALID
15 WU_INT
16–18 —
19–20 CLKIN_SEL[1:0] Select the clock source for the UTMI PHY PLL reference clock. The reference clock can be
21 PHY_CLK_SEL
22 UTMI_PHY_EN
23 PLL_RESET
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
16-44
—
21 22 23
PHY_CLK UTMI_ PLL_
_SEL PHY_EN RESET
Figure 16-34. USB General-Purpose Register (CONTROL)
Table 16-37. CONTROL Field Descriptions
Reserved, must be cleared.
Indicates whether the PHY clock is valid (read only). When in UTMI mode, this bit reflects the value
of the UTMI PHY ClkValid signal. In ULPI mode, this bit reflects the inverted ULPI DIR. In ULPI
mode, this bit is not valid if the USB I/O have not been configured and after the USB_EN signal is
asserted.
0 USB PHY clock is not valid
1 USB PHY clock is valid
Reflects the state of the wake up interrupt. The wake up interrupt signal is asserted when a
wake-up event occurs while in a low-power suspend state. If WU_INT_EN is set, this WU_INT
signal generates an interrupt to the system to indicate wake up servicing is required. WU_INT will
remain set until the USB controller is exited from the low power by clearing the PORTSC[PHCD]
bit.
0 Normal operation or Low Power mode waiting for wakeup event
1 Low power wakeup event has occurred
Reserved, must be cleared.
sourced from the USB_CLK or divide by 1 or 2 of the SYS_CLK. These bits are not relevant when
in ULPI mode.
00 Reference clock is USB_CLK
01 Reference clock is USB_CLK
10 Reference clock is SYS_CLK
11 Reference clock is SYS_CLK divided by 2
Select the source of the USB link controller transceiver clock. When cleared the UTMI PHY is the
source of the clock. When set, the clock is sourced from the external ULPI PHY.
0 UTMI is clock source
1 ULPI is clock source
Enable the UTMI PHY. The UTMI PHY is reset when placed in the disable mode.
0 UTMI PHY disabled
1 UTMI PHY enabled
Reset the UTMI PHY PLL. This bit is not self clearing and must be cleared to complete the reset
sequence.
0 UTMI PHY in normal operating state
1 Put UTMI PHY in reset state
All zeros
24 25 26 27
OTG_ KEEP_
REFSEL
PORT OTG_ON
All zeros
Description
Access: Mixed
13 14
PHY_CLK
WU_INT
_VALID
28 29 30
LSF_ USB_ WU_ ULPI_
EN EN INT_EN INT_EN
Freescale Semiconductor
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