Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 451

— Interrupt-driven block transfer for reads and writes
— Programmable command and data transfer sequences of up to eight steps supported
— Generic command and address registers support proprietary flash interfaces
— Block write locking to ensure system security and integrity
• Three user-programmable machines (UPMs)
— Programmable-array-based machine controls external signal timing with a granularity of up to
one quarter of an external bus clock period
— User-specified control-signal patterns run when an internal master requests a single-beat or
burst read or write access.
— UPM refresh timer runs a user-specified control signal pattern to support refresh
— User-specified control-signal patterns can be initiated by software
— Each UPM can be defined to support DRAM devices with depths of 64, 128, 256, and 512
Kbytes, and 1, 2, 4, 8, 16, 32, 64, 128, and 256 Mbytes
— Support for 8- and 16-bit devices
— Page mode support for successive transfers within a burst
— Internal address multiplexing supporting 64-, 128-, 256-, and 512-Kbyte, and 1-, 2-, 4-, 8-, 16-,
32-, 64-, 128-, and 256-Mbyte page banks
• Optional monitoring of transfers between local bus internal masters and local bus slaves (local bus
error reporting on interrupt and status registers)
10.1.3 Modes of Operation
The eLBC provides one GPCM, one FCM, and three UPMs for the local bus, with no restriction on how
many of the four banks (chip selects) can be programmed to operate with any given machine. The internal
transaction address is limited to 32 bits, so all chip selects must fall within the 4-Gbyte window addressed
by the internal transaction address. When a memory transaction is dispatched to the eLBC, the internal
transaction address is compared with the address information of each bank (chip select). The
corresponding machine assigned to that bank (GPCM, FCM, or UPM) then takes ownership of the external
signals that control the access and maintains control until the transaction ends. Thus, with the eLBC in
GPCM or FCM, or UPM mode, only one of the four chip selects is active at any time for the duration of
the transaction except in the case of UPM refresh where all UPM machines that are enabled for refresh
have concurrent chip select assertion.
10.1.3.1 eLBC Bus Clock and Clock Ratios
The eLBC supports ratios of 2, 4, and 8 between the faster internal (system) clock and slower external bus
clock (LCLK[0:1]). This ratio is software programmable through the clock ratio register
(LCRR[CLKDIV]). This ratio affects the resolution of signal timing shifts in GPCM and FCM modes and
the interpretation of UPM array words in UPM mode. The bus clock is driven identically onto pins,
LCLK[0:1], to allow the clock load to be shared equally across a set of signal nets, thereby enhancing the
edge rates of the bus clock.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Enhanced Local Bus Controller
10-3