Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 589

Table 13-3. PCI Interface Signals—Detailed Signal Descriptions (continued)
Signal I/O
PCI_FRAME I/O PCI cycle frame. Used by the current PCI master to indicate the beginning and duration of an access.
O
I
PCI_GNT0 I/O PCI arbiter grants. Output signal on this PCI controller when the arbiter is enabled. Input signal when
O
I
PCI_GNT[1:2] O
PCI_IDSEL I
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
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Outputs for the bi-directional frame.
State Asserted—The PCI controller acting as a PCI master which is initiating a bus transaction.
Meaning While PCI_FRAME is asserted, data transfers may continue.
Negated—If PCI_IRDY is asserted, indicates that the PCI transaction is in the final data
phase; if PCI_IRDY is negated, indicates that the PCI bus is idle.
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
Inputs for the bi-directional frame.
State Asserted—Another PCI master is initiating a bus transaction.
Meaning Negated—The transaction is in the final data phase or that the bus is idle.
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
the arbiter is disabled.
Note: PCI_GNT[0] is a point-to-point signal. Every master has its own bus grant signal.
Outputs for the bi-directional arbiter grants.
State Asserted—The PCI controller granted control of the PCI bus to agent 0.
Meaning Negated—The PCI controller did not grant control of the PCI bus to agent 0.
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
Inputs for the bi-directional arbiter grants.
State Asserted—The PCI controller has been granted control of the PCI bus by an external
Meaning arbiter.
Negated—The PCI controller has not been granted control of the PCI bus by an external
arbiter.
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
PCI arbiter grants. Output signals on this PCI controller when the arbiter is enabled. Note that
PCI_GNT n is a point-to-point signal. Every master has its own bus grant signal.
Asserted—The PCI controller granted control of the PCI bus to agent n .
State
Meaning Negated—The PCI controller did not grant control of the PCI bus to agent n .
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
PCI initialization device select. Used as a chip select during a PCI configuration cycle in agent mode.
This signal should be tied low in host mode.
State Asserted—The PCI controller is being selected as a target of a configuration read or write
Meaning transactions.
Negated—The PCI controller is not being selected as a target of configuration read or
write transactions.
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
Description
PCI Bus Interface
13-7