Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 521

The RAM array contains 64 words of 32-bits each. The signal timing generator loads the RAM word from
the RAM array to drive the general-purpose lines, byte-selects, and chip-selects. If the UPM reads a RAM
word with WAEN set, the external LUPWAIT signal is sampled and synchronized by the memory
controller and the current request is frozen.
10.4.4.1 UPM Requests
A special pattern location in the RAM array is associated with each of the possible UPM requests. An
internal device's request for a memory access initiates one of the following patterns (M
• Read single-beat pattern (RSS)
• Read burst cycle pattern (RBS)
• Write single-beat pattern (WSS)
• Write burst cycle pattern (WBS)
A UPM refresh timer request pattern initiates a refresh timer pattern (RTS).
An exception (caused by a bus monitor time-out error) occurring while another UPM pattern is running
initiates an exception condition pattern (EXS).
Figure 10-59 and Table 10-39
cycle type. RUN commands (M
UPM RAM words.
Read Single-Beat Request
Read Burst Request
Write Single-Beat Request
Write Burst Request
Refresh Timer Request
Exception Condition Request
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
show the start addresses of these patterns in the UPM RAM, according to
MR[OP] = 11), however, can initiate patterns starting at any of the 64
x
Array Index
Generator
Figure 10-59. RAM Array Indexing
Table 10-39. UPM Routines Start Addresses
UPM Routine
Read single-beat (RSS)
Read burst (RBS)
Write single-beat (WSS)
Write burst (WBS)
RSS
RBS
WSS
RAM Array
WBS
RTS
EXS
Routine Start Address
0x00
0x08
0x18
0x20
Enhanced Local Bus Controller
MR[OP] = 00):
x
64 RAM
Words
10-73