Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 330

e300 Processor Core Overview
7.1.7.3 JTAG Test and Debug Interface
The core provides JTAG and hardware debug functions for facilitating board testing and chip debugging.
The JTAG test interface (based on IEEE 1149.1) provides a means for boundary-scan testing of the core
and the attached system logic. The hardware debug function accesses the JTAG test port, providing a
means for executing test routines and facilitating chip and software debugging.
All instruction and data address breakpoints are accessible in the IBCR and DBCR. See
"Debug Features," for more information.
7.1.7.4 Clock Multiplier
The internal clocking of the e300 core is generated from and synchronized to the external clock signal,
sysclk, by means of a voltage-controlled, oscillator-based PLL. The PLL provides programmable internal
processor clock multiplier ratios which multiply the externally supplied clock frequency. The bus clock is
the same frequency and is synchronous with sysclk. The configuration of the PLL can be read by software
from the hardware implementation register 1 (HID1).
7.1.7.5 Core Performance Monitor
The performance monitor provides the ability to count predefined events and processor clocks associated
with particular operations, such as cache misses, mispredicted branches, or the number of cycles an
execution unit stalls. The count of such events can be used to trigger the performance monitor interrupt.
The performance monitor can be used to do the following:
• Improve system performance by monitoring software execution and then recoding algorithms for
more efficiency. For example, memory hierarchy behavior can be monitored and analyzed to
optimize task scheduling or data distribution algorithms.
• Characterize processors in environments not easily characterized by benchmarking.
• Help system developers bring up and debug their systems.
The performance monitor uses the following resources:
• The performance monitor mark bit in the MSR (MSR[PMM]). This bit controls which programs
are monitored.
• The move to/from performance monitor registers (PMR) instructions, mtpmr and mfpmr.
• The external core input, pm_event_in.
• PMRs:
— The performance monitor counter registers (PMC0–PMC3) are 32-bit counters used to count
software-selectable events. Each counter counts up to 128 events. UPMC0–UPMC3 provide
user-level read access to these registers. They are identified in
— The performance monitor global control register (PMGC0) controls the counting of
performance monitor events. It takes priority over all other performance monitor control
registers. UPMGC0 provides user-level read access to PMGC0.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
7-12
Section 7.3.8,
Table 7-2.
Freescale Semiconductor