Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 571

Bits Name
3 TEM Transfer error mask. This bit determines the DMA response in the event of a transfer error.
0 The DMA will halt when a transfer error occurs.
1 The DMA will complete the transfer regardless of whether a transfer error occurs.
Note: Regardless of the setting of TEM, if an error condition was detected during the DMA transfer, it will
2 CTM Channel transfer mode.
0 Chaining mode
1 Direct mode
1 CC Channel continue. This bit applies only to chaining mode. Setting this bit indicates that the current
descriptor segment should be repeated. CC is cleared by the DMA once the repeat takes effect, so it only
causes a single repeat.
0 Normal chaining
1 DMACDAR is not loaded from DMANDAR, causing a repeat of the current descriptor segment
0 CS Channel start. A 0-to-1 transition occurring on this bit when the channel is not busy (SR[CB] bit is 0) will
start the DMA process. If the channel is busy and a 0-to-1 transition occurs, the DMA channel will restart
from a previous halt condition. A 1-to-0 transition when the channel is busy (CB bit is 1) will halt the DMA
process. Nothing happens if the channel is not busy and a 1-to-0 transition occurs. This bit is cleared by the
DMA at the end of a transfer.
12.3.8.2 DMA Status Register (DMASR n )
This section describes the DMA status register. The status register reports various DMA conditions during
and after the DMA transfer. Writing a 1 to a specific set bit clears the bit.
fields.
Offset 0x104, 0x184, 0x204, 0x284
31
R
W
Reset
Table 12-11 describes the DMASRn register.
Bits Name
31–8 — Reserved
7 TE Transfer error. Set when there is an error condition during the DMA transfer.
6–3 — Reserved
2 CB Channel busy. This bit indicates whether the channel is busy. It is cleared as a result of any of the following
conditions: an error or completion of the DMA transfer.
0 No DMA transfer is currently in progress
1 A DMA transfer is currently in progress
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 12-10. DMAMR n Field Descriptions (continued)
cause DMASR n [TE] to be set.
—
Figure 12-11. DMA Status Register (DMASR n )
Table 12-11. DMASR n Field Descriptions
Description
Figure 12-11
8 7
TE
All zeros
Description
DMA/Messaging Unit
shows the DMASRn
Access: User Mixed
6 3 2 1
CB
Ò EOSI EOCDI
0
12-11