Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 317

The transaction with an address only transfer type, the arbiter performs as follows:
1. Ends the address tenure by asserting AACK.
2. Reports on the event to AER[AO].
3. Issues reset request, MCP or regular interrupt according to AERR[AO] and AIDR[AO] if enabled
by AMR[AO].
4. Updates transaction attributes and address of AEATR and AEADR for the first error event.
6.3.2.5 Reserved Transaction Type
Table 6-11 shows transaction types defined as reserved.
The transaction with a reserved transfer type, the arbiter performs as follows:
1. Ends the address tenure by asserting AACK.
2. Reports on the event to AER[RES].
3. Issues reset request, MCP or regular interrupt according to AERR[RES] and AIDR[RES], if
enabled by AMR[RES].
4. Updates transaction attributes and address of AEATR and AEADR for the first error event.
6.3.2.6 Illegal (eciwx/ecowx) Transaction Type
Table 6-12 shows transaction types defined as illegal.
The transaction with an illegal (eciwx, ecowx) transfer type, the arbiter performs as follows:
1. Ends the address tenure by asserting AACK.
2. Starts data tenure and ends data tenure by asserting TEA.
3. Reports on the event in AER[ECW].
4. Issues reset request, MCP or regular interrupt according to AERR[ECW] and AIDR[ECW], if
enabled by AMR[ECW].
5. Updates transaction attributes and address of AEATR and AEADR for the first error event.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 6-11. Reserved Transaction Type Encoding
ttype[0:4]
00101
1xx01
10110
00011
00111
01111
1xx11
Table 6-12. Illegal Transaction Type Encoding
ttype[0:4]
10100 External control word write (ecowx)
11100 External control word read (eciwx)
Bus Commands
Reserved
Reserved for customer
Reserved
Reserved
Reserved
Reserved
Reserved for customer
Bus command
Arbiter and Bus Monitor
6-15