Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 780

Enhanced Three-Speed Ethernet Controllers
15.5.3.3.10 Receive Data Buffer Pointer High Register (RBDBPH)
The RBDBPH register is written by the user with the most significant address bits common to all RxBD
buffer addresses, RxBD[Data Buffer Pointer]. As a consequence, Rx buffers must be placed in a 4 Gbyte
segment of memory whose base address is prefixed by the bits in RBDBPH. The RxBD ring itself can
reside in a different memory region (based at RBASEH).
RBDBPH register.
Offset eTSEC1:0x2_4380; eTSEC2:0x2_5380
0
R
W
Reset
Table 15-36 describes the fields of the RBDBPH register.
Bits Name
0–27 — Reserved
28–31 RBDBPH Most significant bits common to all data buffer addresses contained in RxBDs. The user must initialize
RBDBPH before enabling the eTSEC receive function.
15.5.3.3.11 Receive Buffer Descriptor Pointers 0–7 (RBPTR0–RBPTR7)
RBPTR0–RBPTR7 each contains the low-order 32 bits of the next receive buffer descriptor address for
their respective RxBD ring.
value of their ring's associated RBASE when the RBASE register is written by software. Software must
not write RBPTRn while eTSEC is actively receiving frames. However, RBPTRn can be modified when
the receiver is disabled or when no Rx buffer is in use (after a GRACEFUL STOP RECEIVE command is
issued and the frame completes its reception) in order to change the next RxBD eTSEC receives.
Offset eTSEC1:0x2_4384+8× n ; eTSEC2:0x2_5384+8× n
0
R
W
Reset
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
15-62
Figure 15-32. RBDBPH Register Definition
Table 15-36. RBDBPH Field Descriptions
Figure 15-33 describes the RBPTR registers. These registers takes on the
RBPTR n
Figure 15-33. RBPTR0–RBPTR7 Register Definition
Figure 15-32 describes the definition for the
—
All zeros
Description
All zeros
Access: Read/Write
27 28 31
RBDBPH
Access: Read/Write
28 29 31
—
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