Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 314

Arbiter and Bus Monitor
• M0 and M3 each gets 1/18 of the bus bandwidth
• M1 and M2 each gets 1/36 of the bus bandwidth
Z
Y
X
Figure 6-10. An Example of Priority-Based Arbitration Algorithm
See each bus master's chapter and
Configuration Register
programming.
6.3.1.2 Address Bus Arbitration with REPEAT
When a master owns the address bus and wants to perform another transaction, it can assert bus request
along with REPEAT, to make a repeat request to the arbiter. Consequently, the arbiter asserts bus grant to
the same master if the current address tenure is not being ARTRYed. This happens regardless of the priority
level of bus request from other masters. In another word, "repeat request" overrides the priority scheme.
Even though repeat request can improve the page hit ratio and the overall memory bandwidth efficiency,
it can increase the worst case latency of individual master. Therefore, the arbiter has programmable
counter to limit the maximum number of consecutive transactions that are performed by masters.
Whenever the counter expires, arbiter ignores the REPEAT signal and falls back to the regular arbitration
scheme. PCI master has a dedicated repeat counter as it might need more repeated transactions before
accepting read requests. PCI ordering rules require that the PCI bridge should empty all queued write
operations before any new read operation can begin. See Section 3.2.5, "Transaction Ordering and
Posting," of the PCI Local Bus Specifications Rev 2.2, for more information.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
6-12
Level 3
M6
Level 2
M4 M5
Level 1
M0 M3
Level 0
M1 M2
NOTE
Section 5.3.2.4, "System Priority and
(SPCR)," for more details about priority
M6 Z M6 Z ...
M6 M4 M6 M5 M6 M0 M6 M4
M6 M5 M6 M3 M6 M4 M6 M5
M6 M1 M6 M4 M6 M5 M6 M0
M6 M4 M6 M5 M6 M3 M6 M4
M6 M5 M6 M2 ...
M4 M5 Y M4 M5 Y ...
M4 M5 M0 M4 M5 M3 M4 M5 M1
M4 M5 M0 M4 M5 M3 M4 M5 M2 ...
M0 M3 X M0 M3 X ...
M0 M3 M1 M0 M3 M2 M0 M3 M1 ...
M1 M2 M1 M2 ...
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