Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 913

Table 15-167. MII Mode Register Initialization Steps (continued)
Set up the MII Mgmt for a write cycle to the external PHY Extended PHY control register #1 to set up the interface mode
Write to MII Mgmt Control with 16-bit data intended for the external PHY register,
Set up the MII Mgmt for a write cycle to the external PHY Mode control register to set up the interface mode selection.
Write to MII Mgmt Control with 16-bit data intended for the external PHY register,
If auto-negotiation was enabled in the PHY, check to see if PHY has completed Auto-Negotiation.
Set up the MII Mgmt for a read cycle to PHY MII Mgmt register (write the PHY address and Register address),
The PHY Status register is at address 0x1 and in this case the PHY Address is 0x00.
(Uses the PHY address (0) and Register address (1) placed in MIIMADD register),
Other information about the link is also returned.(Extend Status, No pre, Remote Fault, An Ability, Link status, extend Ability)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Check to see if MII Mgmt write is complete
Read MII Mgmt Indicator register and check for Busy = 0,
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
This indicates that the write cycle was completed.
MIIMADD[0000_0000_0000_0000_0000_0000_0001_0111]
Perform an MII Mgmt write cycle to the external PHY.
MIIMCON[0000_0000_0000_0000_0000_0000_0000_0000]
Check to see if MII Mgmt write is complete.
Read MII Mgmt Indicator register and check for Busy = 0,
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
This indicates that the write cycle was completed.
MIIMADD[0000_0000_0000_0000_0000_0000_0000_0000]
Perform an MII Mgmt write cycle to the external PHY.
MIIMCON[0000_0000_0000_0000_00uu_00uu_0u00_0000]
where u is user defined based on desired configuration.
Check to see if MII Mgmt write is complete
Read MII Mgmt Indicator register and check for Busy = 0,
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
This indicates that the write cycle was completed.
MIIMADD[0000_0000_0000_0000_0000_0000_0000_0001]
Perform an MII Mgmt read cycle of Status Register.
Clear MIIMCOM[Read Cycle].
Set MIIMCOM[Read Cycle].
When MIIMIND[BUSY]=0,
read the MIIMSTAT register and check bit 10 (AN Done and Link is up)
MIIMSTAT ---> [0000_0000_0000_0000_0000_0000_0010_0100]
Check auto-negotiation attributes in the PHY as necessary.
Clear IEVENT register,
IEVENT[0000_0000_0000_0000_0000_0000_0000_0000]
Initialize IMASK (Optional)
IMASK[0000_0000_0000_0000_0000_0000_0000_0000]
Initialize MACnADDR1/2 (Optional)
MACnADDR1/2[0000_0000_0000_0000_0000_0000_0000_0000]
Initialize GADDR n (Optional)
GADDR n [0000_0000_0000_0000_0000_0000_0000_0000]
Initialize RCTRL (Optional)
RCTRL[0000_0000_0000_0000_0000_0000_0000_0000]
Enhanced Three-Speed Ethernet Controllers
selection.
15-195