Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 272

System Configuration
• Pair-cascaded mode (GTCFR1[PCAS] = 1 and/or GTCFR2[PCAS] = 1, GTCFR2[SCAS] = 0)
In this mode, two 16-bit timers can be internally cascaded to form a 32-bit counter: timer 1 may be
internally cascaded to timer 2 and timer 3 may be internally cascaded to timer 4, as shown in
Figure 5-49. Since the decision to cascade timers is made independently, the user has the option of
selecting two 16-bit timers and one 32-bit timer (GTCFR1[PCAS] = 1, GTCFR2[PCAS] = 0 or
GTCFR1[PCAS1] = 0, GTCFR2[PCAS] = 1), or two 32-bit timers (GTCFR1[PCAS] = 1 and
GTCFR2[PCAS] = 1).
If GTCFR1[PCAS] = 1 and/or GTCFR2[SCAS] = 1, the two 16-bit timers (timer 1 and timer 2 or
timer 3 and timer 4) function as a 32-bit timer with a 32-bit GTRFR, GTCPR, and GTCNR. In this
case, GTMDR1/GTMDR3 is ignored, and the modes and functions are defined using
GTMDR2/GTMDR4, and GTCFR1/GTCFR2. The capture are controlled from TIN2, and the
interrupts are generated from GTEVR2. When working in the pair-cascaded mode, the cascaded
GTRFR, GTCPR, and GTCNR should be referenced with 32-bit bus cycles.
GTRFR1, GTCPR1, GTCNR1
connected to D[31–16]
GTRFR3, GTCPR3, GTCNR3
connected to D[31–16]
• Super-cascaded mode (GTCFR2[SCAS] = 1)
In this mode, all four 16-bit timers can be internally cascaded to form a 64-bit counter, as shown
in Figure 5-50.
If GTCFR2[SCAS] = 1, the all four 16-bit timers function as a 64-bit timer with a cascaded 32-bit
GTRFR, GTCPR, and GTCNR. In this case, registers GTMDR1, GTMDR2, GTMDR3, and
GTCFR1 are ignored, and the modes and functions are defined using GTMDR4 and GTCFR2 only.
The capture are controlled from TIN4, and the interrupts are generated from GTEVR4. When
working in the super-cascaded mode, the cascaded GTRFR, GTCPR, and GTCNR should be
referenced with two 32-bit bus cycles.
GTRFR1, GTCPR1, GTCNR1
connected to D[63–48]
GTRFR3, GTCPR3, GTCNR3
connected to D[31–16]
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
5-64
Timer1
Timer3
Figure 5-49. Timer Pair-Cascaded Mode Block Diagram
Timer1
Timer3
Figure 5-50. Timers Super-Cascaded Mode Block Diagram
Timer2
GTRFR2, GTCPR2, GTCNR2
connected to D[15–0]
Timer4
GTRFR4, GTCPR4, GTCNR4
connected to D[15–0]
Timer2
GTRFR2, GTCPR2, GTCNR2
connected to D[47–32]
Timer4
GTRFR4, GTCPR4, GTCNR4
connected to D[15–0]
Clock
Capture
Clock
Capture
Clock
Capture
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