Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 949

Note that this register is shared between the host and device mode functions. In host mode, it is the
ASYNCLISTADDR register; in device mode, it is the ENDPOINTLISTADDR register. See
Section 16.3.2.9, "Endpoint List Address Register (ENDPOINTLISTADDR)—Non-EHCI,"
information.
Offset 0x2_3158
31
R
W
Reset
Figure 16-14. Current Asynchronous List Address (ASYNCLISTADDR)
Bits Name
31–5 ASYBASE Link pointer low (LPL). These bits correspond to memory address signals [31:5]. This field may only
reference a queue head (QH). Only used by the host controller.
4–0 — Reserved, should be cleared.
16.3.2.9 Endpoint List Address Register (ENDPOINTLISTADDR)—Non-EHCI
This register is not defined in the EHCI specification. In device mode, this register contains the address of
the top of the endpoint list in system memory. Bits 10–0 of this register cannot be modified by the system
software and always return zeros when read. The memory structure referenced by this physical memory
pointer is assumed to be 64-bytes. The queue head is actually a 48-byte structure, but must be aligned on
64-byte boundary. However, the ENDPOINTLISTADDR[EPBASE] has a granularity of 2 Kbytes, so in
practice the queue head should be 2-Kbyte aligned.
Note that this register is shared between the host and device mode functions. In device mode, it is the
ENDPOINTLISTADDR register; in host mode, it is the ASYNCLISTADDR register. See
Section 16.3.2.8, "Current Asynchronous List Address Register (ASYNCLISTADDR),"
information.
Offset 0x2_3158
31
R
W
Reset
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
ASYBASE
Table 16-17. ASYNCLISTADDR Register Field Descriptions
EPBASE
Figure 16-15. Endpoint List Address (ENDPOINTLISTADDR)
All zeros
Description
11 10
All zeros
Universal Serial Bus Interface
for more
Access: Read/Write
5 4 0
—
for more
Access: Read/Write
0
—
16-21