Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 800

Enhanced Three-Speed Ethernet Controllers
15.5.3.6.5 Transmit and Receive 512- to 1023-Byte Frame Counter (TR1K)
Figure 15-56 shows the TR1K register.
Offset eTSEC1:0x2_4690; eTSEC2:0x2_5690
0
R
W
Reset
Figure 15-56. Transmit and Received 512- to 1023-Byte Frame Register Definition
Table 15-60 describes the fields of the TR1K register.
Bits Name
0–9 — Reserved
10–31 TR1K Increments for each good or bad frame transmitted and received which is 512–1023 bytes in length, inclusive
(excluding preamble and SFD but including FCS bytes).
15.5.3.6.6 Transmit and Receive 1024- to 1518-Byte Frame Counter (TRMAX)
Figure 15-57 describes the definition for the TRMAX register.
Offset eTSEC1:0x2_4694; eTSEC2:0x2_5694
0
R
W
Reset
Figure 15-57. Transmit and Received 1024- to 1518-Byte Frame Register Definition
Table 15-61 describes the fields of the TRMAX register.
Bits Name
0–9 — Reserved
10–31 TRMAX Increments for each good or bad frame transmitted and received which is 1024–1518 bytes in length,
inclusive (excluding preamble and SFD but including FCS bytes).
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
15-82
9 10
—
Table 15-60. TR1K Field Descriptions
9 10
—
Table 15-61. TRMAX Field Descriptions
TR1K
All zeros
Description
TRMAX
All zeros
Description
Access: Read/Write
31
Access: Read/Write
31
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