Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 170

Reset, Clocking, and Initialization
Signal I/O
USB_CR_CLK_OUT O
PCI_CLK/ I
PCI_SYNC_IN
PCI_SYNC_OUT O
PCI_CLK_OUT[0:2] O
4.2 Functional Description
This section describes the various ways to reset the device, the power-on reset configurations, and
clocking.
4.2.1 Reset Operations
The device has several inputs to the reset logic:
• Power-on reset (PORESET)
• External hard reset (HRESET)
• External soft reset (SRESET)
• Software watchdog reset
• System bus monitor reset
• Checkstop reset
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
4-4
Table 4-2. External Clock Signals (continued)
USB crystal output. USB_CR_CLK_IN/USB_CR_CLK_OUT allows the USB clock to be provided
through an external crystal oscillator. If a crystal source is used, USB_CLK_IN should be tied low.
Timing Assertion/Negation—See the hardware specifications for timing information
Requirements Should be left unconnected if unused, for example when the clock is provided
through USB_CR_CLK_IN or when derived from the system clock.
Reset State Always output.
PCI clock/ PCI synchronization clock (PCI_CLK/PCI_SYNC_IN). PCI_CLK is the primary clock
input to the device, the reference clock for the system APLL. When the device is in PCI host mode
SYS_CLK_IN or SYS_CR_CLK_IN is used as the clock source. In this case the
PCI_CLK_OUT[0:2] signals are driven and PCI_SYNC_IN should be tied to PCI_SYNC_OUT.
When the device is in PCI agent mode PCI_CLK will be tied directly to a PCI system clock source.
Timing Assertion/Negation—See the hardware specifications for timing information
Reset State Always input.
Reference PCI output synchronization clock (PCI_SYNC_OUT). In PCI host mode with the
PCI_CLK_OUT[0:2] signals driven, PCI_SYNC_OUT is connected externally to PCI_SYNC_IN
signal for de-skewing external PCI clocks routing. PCI_SYNC_OUT has the same frequency as
CLKIN or CLKIN/2 depending on the state of CFG_CLKIN_DIV at reset. See
"SYS_CLK_IN Division." In PCI agent mode, this signal is typically not used.
Timing Assertion/Negation—See the hardware specifications for timing information.
Reset State Always output, toggling in PCI host mode.
PCI output clocks bank. In PCI host mode, the device provides three separate clock output signals
for feeding PCI agent devices.
Timing Assertion/Negation—See the hardware specifications for timing information.
Reset State Always output. Drive '0' and after power-on reset flow. Enabled by a
memory-mapped register.
Description
Section 4.3.1.2,
Freescale Semiconductor